-- ************************************************************************
--  - H/W Development Group
-- ************************************************************************
--
--  Title:     alu8bit
--
--  Created:   Fri Aug 25 11:42:48 2000
--  Author:                   Deeapk George
--  Source File Name:   alu8bit.vhd
--
--  $Id: alu8bit.vhd,v 1.1 2000/08/25 11:42:48 acts Exp $
--
--  Description:   8 bit ALU
--
--  Revision History:  
--
--  $Log: alu8bit.vhd,v $
--
-- ************************************************************************
library IEEE, STD;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_components.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_misc.all;
use IEEE.std_logic_unsigned.all;
entity alu8bit is
port ( inst : in std_logic_vector ( 7 downto 0);--   OPCODE and DATA
       clk  : in std_logic;              --   Clock
       rst  : in std_logic);             --   Reset
end alu8bit;
architecture alu8bit_A of alu8bit is
signal regA             : std_logic_vector(7 downto 0);--   Reg A
signal regB             : std_logic_vector(7 downto 0);--   Reg B
signal regC             : std_logic_vector(7 downto 0);--   Reg C
signal regD             : std_logic_vector(7 downto 0);--   Reg D
signal d                : std_logic_vector(1 downto 0);--   Store MVI Addr.
signal count            : std_logic;     --   Count for MVI Inst.
begin
compute : process(rst,clk,inst)
---------------------------------------------------------------------------
--  Internal Interconnections
---------------------------------------------------------------------------
  variable a                : std_logic_vector(7 downto 0);
  variable b                : std_logic_vector(7 downto 0);
  variable c                : std_logic_vector(7 downto 0);
begin
if (rst = '1') then
  regA <= (others => '0');
  regB <= (others => '0');
  regC <= (others => '0');
  regD <= (others => '0');
  count <= '0';
  d    <= (others => '0');
 
  else
  -----------------------------------------------------------------------
    -- Source the contents of the source register.  
  -----------------------------------------------------------------------
  case inst(1 downto 0) is
   
    when "00" =>
      a:= regA;
     
    when "01" =>
     a:= regB;
     
    when "10" =>
     a:= regC;
     
    when others  =>
     a:= regD;
  end case;
 
  -----------------------------------------------------------------------
  -- Source the contents of the Destination Registers
  -----------------------------------------------------------------------
  case inst(3 downto 0) is
 
    when "00" =>
      b:= regA;
     
    when "01" =>
     b:= regB;
     
    when "10" =>
     b:= regC;
     
    when others =>
     b:= regD;
  end case;
  -------------------------------------------------------------------------
  --  Perform ALU operations
  -------------------------------------------------------------------------
  case inst( 7 downto 4) is
    when "0001" =>                       --   And dest, src
      c:= a and b;
     
    when "0010" =>                       --   Mov dest, src
      c:= a;
     
    when "0011" =>                       --   INC src
      c:= a +1;
     
    when "0100" =>                       --   Dec src
      c:= a -1;
     
    when "0101" =>                       --   ADD dest, src
      c:= a+b;
     
    when "0110" =>                       --   SUB dest, src
      c:= a-b;
     
    when "0111" =>                       --   SHL src
   
      c(0) <= a(7);
      c(1) <= a(0);
      c(2) <= a(1);
      c(3) <= a(2);
      c(4) <= a(3);
      c(5) <= a(4);
      c(6) <= a(5);
      c(7) <= a(6);
     
    when "1001" =>                       --   SHR src
      c(0) <= a(1);
      c(1) <= a(2);
      c(2) <= a(3);
      c(3) <= a(4);
      c(4) <= a(5);
      c(5) <= a(6);
      c(6) <= a(7);
      c(7) <= a(0);
     
    when "1010" =>                       --   MVI src
   
    if (clk'event and clk = '1') then
      count <= count +1;
      d<= inst ( 3 downto 0);
      c:= inst;
    end if;
   
    when others =>
    accu <= ( others => '0'); 
  end case;
end if;
---------------------------------------------------------------------------
--  Store the Results
---------------------------------------------------------------------------
if (clk'event and clk = '1') then
  -------------------------------------------------------------------------
  -- Storing Result for MVI instruction
  -------------------------------------------------------------------------
  if (count = '1') then
    c:= inst;
    count <= count +1;
   
    case d is
      when "00" =>
        regA <= c;
      when "01" =>
        regB <= c;
      when "10" =>
        regC <= c;
      when others  =>
        regD <= c;
    end case;
  else
  -------------------------------------------------------------------------
  --  Storing Result for other instructions
  -------------------------------------------------------------------------
    accu <= c;
    case inst(3 downto 0) is
      when "00" =>
        reg A <= c;
      when "01" =>
        regB <= c;

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OR

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      when "10" =>
        regC <= c;
      when others =>
        regD <= c;
    end case;
   
  end if;
end if;
 
end process;
end alu8bit_A;