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-- ************************************************************************ |
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-- - H/W Development Group |
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-- ************************************************************************ |
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-- |
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-- Title: alu8bit |
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-- |
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-- Created: Fri Aug 25 11:42:48 2000 |
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-- Author: Deeapk George |
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-- Source File Name: alu8bit.vhd |
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-- |
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-- $Id: alu8bit.vhd,v 1.1 2000/08/25 11:42:48 acts Exp $ |
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-- |
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-- Description: 8 bit ALU |
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-- |
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-- Revision History: |
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-- |
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-- $Log: alu8bit.vhd,v $ |
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-- |
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-- ************************************************************************ |
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library IEEE, STD; |
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use IEEE.std_logic_1164.all; |
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use IEEE.std_logic_components.all; |
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use IEEE.std_logic_arith.all; |
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use IEEE.std_logic_misc.all; |
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use IEEE.std_logic_unsigned.all; |
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entity alu8bit is |
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port ( inst : in std_logic_vector ( 7 downto 0);-- OPCODE and DATA |
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clk : in std_logic; -- Clock |
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rst : in std_logic); -- Reset |
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end alu8bit; |
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architecture alu8bit_A of alu8bit is |
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signal regA : std_logic_vector(7 downto 0);-- Reg A |
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signal regB : std_logic_vector(7 downto 0);-- Reg B |
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signal regC : std_logic_vector(7 downto 0);-- Reg C |
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signal regD : std_logic_vector(7 downto 0);-- Reg D |
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signal d : std_logic_vector(1 downto 0);-- Store MVI Addr. |
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signal count : std_logic; -- Count for MVI Inst. |
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begin |
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compute : process(rst,clk,inst) |
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--------------------------------------------------------------------------- |
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-- Internal Interconnections |
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--------------------------------------------------------------------------- |
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variable a : std_logic_vector(7 downto 0); |
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variable b : std_logic_vector(7 downto 0); |
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variable c : std_logic_vector(7 downto 0); |
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begin |
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if (rst = '1') then |
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regA <= (others => '0'); |
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regB <= (others => '0'); |
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regC <= (others => '0'); |
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regD <= (others => '0'); |
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count <= '0'; |
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d <= (others => '0'); |
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else |
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----------------------------------------------------------------------- |
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-- Source the contents of the source register. |
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----------------------------------------------------------------------- |
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case inst(1 downto 0) is |
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when "00" => |
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a:= regA; |
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when "01" => |
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a:= regB; |
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when "10" => |
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a:= regC; |
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when others => |
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a:= regD; |
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end case; |
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----------------------------------------------------------------------- |
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-- Source the contents of the Destination Registers |
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----------------------------------------------------------------------- |
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case inst(3 downto 0) is |
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when "00" => |
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b:= regA; |
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when "01" => |
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b:= regB; |
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when "10" => |
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b:= regC; |
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when others => |
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b:= regD; |
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end case; |
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------------------------------------------------------------------------- |
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-- Perform ALU operations |
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------------------------------------------------------------------------- |
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case inst( 7 downto 4) is |
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when "0001" => -- And dest, src |
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c:= a and b; |
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when "0010" => -- Mov dest, src |
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c:= a; |
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when "0011" => -- INC src |
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c:= a +1; |
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when "0100" => -- Dec src |
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c:= a -1; |
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when "0101" => -- ADD dest, src |
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c:= a+b; |
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when "0110" => -- SUB dest, src |
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c:= a-b; |
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when "0111" => -- SHL src |
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c(0) <= a(7); |
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c(1) <= a(0); |
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c(2) <= a(1); |
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c(3) <= a(2); |
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c(4) <= a(3); |
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c(5) <= a(4); |
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c(6) <= a(5); |
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c(7) <= a(6); |
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when "1001" => -- SHR src |
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c(0) <= a(1); |
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c(1) <= a(2); |
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c(2) <= a(3); |
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c(3) <= a(4); |
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c(4) <= a(5); |
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c(5) <= a(6); |
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c(6) <= a(7); |
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c(7) <= a(0); |
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when "1010" => -- MVI src |
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if (clk'event and clk = '1') then |
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count <= count +1; |
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d<= inst ( 3 downto 0); |
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c:= inst; |
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end if; |
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when others => |
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accu <= ( others => '0'); |
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end case; |
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end if; |
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--------------------------------------------------------------------------- |
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-- Store the Results |
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--------------------------------------------------------------------------- |
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if (clk'event and clk = '1') then |
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------------------------------------------------------------------------- |
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-- Storing Result for MVI instruction |
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------------------------------------------------------------------------- |
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if (count = '1') then |
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c:= inst; |
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count <= count +1; |
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case d is |
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when "00" => |
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regA <= c; |
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when "01" => |
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regB <= c; |
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when "10" => |
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regC <= c; |
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when others => |
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regD <= c; |
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end case; |
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else |
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------------------------------------------------------------------------- |
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-- Storing Result for other instructions |
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------------------------------------------------------------------------- |
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accu <= c; |
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case inst(3 downto 0) is |
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when "00" => |
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reg A <= c; |
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when "01" => |
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regB <= c; |
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If you have any suggestions or modifications to this code , please send them to me at :
deepak.g@angelfire.com
OR
Put them on my guest book below , i will test them and add it with your name. |
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when "10" => |
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regC <= c; |
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when others => |
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regD <= c; |
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end case; |
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end if; |
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end if; |
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end process; |
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end alu8bit_A; |
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