--************************************************************************

--  - H/W Development Group

-- ************************************************************************

--

--  Title:     256*8 Contant Access Memory (CAM)

--

--  Created:   Mon Aug 28 12:14:47 2000

--  Author:                DEEPAK GEORGE

--  Source File Name:   cam256.vhd

--

--  $Id: cam256.vhd,v 1.1 2000/08/28 12:14:47 acts Exp $

--

--  Description:   This is the code for a Content Access Type of memory,

--   it has got a 256*8 bit TAG table and a 256*8 Data table. CAM 

--   will match the contents of the TAG with the datain and if a match is

--   found HIT is made high and the appropriate data is outputed on the

--   dataout port.

--

--  Revision History:  

--

--  $Log: cam256.vhd,v $

--

-- ************************************************************************

 

library IEEE, STD;

use IEEE.std_logic_1164.all;

use IEEE.std_logic_components.all;

use IEEE.std_logic_arith.all;

use IEEE.std_logic_misc.all;

use IEEE.std_logic_unsigned.all;

 

entity cam256 is

  port     (clk              : in   std_logic;                   --   Clock

            rst              : in   std_logic;                   --   Reset

            rd_b             : in   std_logic;                   --   Read

            wr_b             : in   std_logic;                   --   Write

            datain           : in   std_logic_vector(7 downto 0);-- data in

                                                                 -- during write.

            tagin            : in   std_logic_vector(7 downto 0);-- Tag Data

            data_out         : out  std_logic_vector(7 downto 0);-- Data out

            full             : out  std_logic;                   -- Stack Full  

            hit              : out  std_logic                    -- Found Match  

           );

end cam256;

 

 

architecture cam256_A of cam256 is

type ram_array is aray (0 to 255 ) of std_logic_vector(7 downto 0);

signal tag              : ram_array;

signal data             : ram_array;

signal count            : integer range 0 to 255;

begin

 

main : process(clk,rst)

 

begin

  if (rst = '1') then

    tag<=(others=>'0');

    data<=(others=>'0');

    count<= 0;

    full <= '0';

 -----------------------------------------------------------------------

 --  Stack Write Operation

 -----------------------------------------------------------------------

  elsif ( clk'evevt and clk='1') then

    if (wr_b = '0' and rd_b = '1') then

      if ( count = 255 ) then

        full <= '1';

      else

        tag (conv_integer (count))<= tin;

        data(conv_integer (count))<= datain;

        count <= count +1;

      end if;

---------------------------------------------------------------------------

--  Stack CAM Read  Operation

---------------------------------------------------------------------------

    elsif (wr_b = '1' and rd_b = '0') then

      for addr 0 to 255 loop             --   Check for data

        if ( tagin = tag(conv_integer (addr)) then

          Hit <= '1';                    --   Found Match

          data_out <= data ( conv_integer (addr));

        else

          hit <= '0';                    --   No match found

        end if;

      end loop;

    end if 

  end if;

end process; 

 

end cam256_A;