NOTE
:
The code for FIFO Using DPRAM is given here the code
for the DPRAM is given after that.
--**********************************************************************
-- - H/W Development Group
--
--**********************************************************************
--
-- Title:
FIFO Using DPRAM
--
-- Created:
Wed Aug 30 14:54:17 2000
-- Author: Deepak George
-- Source File Name: fifo2.vhd
--
-- $Id: fifo2.vhd,v 1.1 2000/08/30 14:54:17 acts
Exp $
--
-- Description: This is the code for a FIFO Using a DPRAM, here the
-- Read and write signals should not occur
simultaneously.
--
-- Revision History: rev 1.0
--
-- $Log: fifo2.vhd,v $
--
--
************************************************************************
library
IEEE, STD;
use
IEEE.std_logic_1164.all;
use
IEEE.std_logic_components.all;
use
IEEE.std_logic_arith.all;
use
IEEE.std_logic_misc.all;
use
IEEE.std_logic_unsigned.all;
entity
fifo is
port
(clk : in std_logic;--CLOCK
rst : in
std_logic;--Reset
rd : in
std_logic;-- RD Active L
wr : in
std_logic;-- WR Active L
data1 : inout
std_logic_vector(7 downto 0);--Data WR
data2 : inout std_logic_vector(7 downto 0);--Data RD
full : out
std_logic;-- FIFO FULL
p_full : out
std_logic;-- FIFO Partially
Full(>240)
p_epty : out
std_logic;-- FIFO Partially
Empty(<15)
epty : out
std_logic -- FIFO EMPTY
);
end
fifo;
architecture
fifo_A of fifo is
component dpram
port
(clk : in std_logic; -- Clock
addr1 : in
std_logic_vector (7 downto 0); -- Address1
addr2 : in
std_logic_vector (7 downto 0); -- Address2
data1 : inout
std_logic_vector(7 downto 0); -- Data Port1
data2 : inout std_logic_vector(7 downto 0); -- Data Port2
rd_b : in
std_logic;
--Read0
wr_b : in
std_logic
--Write0
);
end component;
signal W_add : std_logic_vector(7 downto 0);-- Write Addr Gen
signal R_add : std_logic_vector(7 downto 0);-- Read Addr Gen
signal C_add :
std_logic_vector(7 downto 0);-- Check
Count
signal wri : std_logic;
-- Internal Write Enable
signal rdi : std_logic;
-- Internal Read Enable
signal fulli : std_logic;
signal p_fulli : std_logic;
signal p_eptyi : std_logic;
signal eptyi : std_logic;
begin
U1
: port map dpram(clk => clk,
addr1=> w_add,
addr2=> r_add,
data1=> data1,
data2=> data2,
rd_b => rdi,
wr_b => wri
);
-- Write Enable on getting a WR input and if
FIFO is not full
wri <= '0' when (wr = '0' and fulli = '0')
else '1';
-- Read Enable on getting a RD input and if
FIFO is not empty
rdi <= '0' when (rd = '0' and eptyi = '0')
else '1';
---------------------------------------------------------------------------
-- Issue FIFO Status Signals
---------------------------------------------------------------------------
fulli <= '1' when (c_add =
"11111111") else '0';-- Full
if C_add= 255
eptyi <= '1' when (c_add =
"00000000") else '0';--
Empty if C_add = 0
p_fulli
<= '1' when (c_add > "11110000") else '0';-- Part full if C_add >240
p_eptyi
<= '1' when (c_add < "00000111") else '0';-- Part Empty if C_add<15
---------------------------------------------------------------------------
-- Genrate Write and Read Address
---------------------------------------------------------------------------
main
: process(clk,rst)
begin
if ( rst = '1') then
w_add
<= (others => '0');
r_add
<= (others => '0');
c_add
<= (others => '0');
elsif (clk'event and clk = '1') then
-------------------------------------------------------------------------
--
FIFO write , when w_add is 255 and if full = 0 then the writing will
--
start from 0 addr location again.
-------------------------------------------------------------------------
if (wri = '0') then -- FIFO Write Operation
w_add <= w_add + 1;
if (rdi = '0') then
c_add <= c_add;
else
c_add <= c_add + 1;
end if;
end if;
if (rdi = '0') then -- FIFO Read
Operation
r_add <= r_add +1;
if (wri <= '0') then
c_add <= c_add;
else
c_add <= c_add -1;
end if;
end if;
end
process;
full <= fulli;
epty <= eptyi;
p_full<=
p_fulli;
p_epty<=
p_epty;
end
fifo_A;
END
OF FIFO
FIFO OPTIMIZED (
Optimization done for Comparator’s)
--
************************************************************************
-- - H/W Development Group
-- ************************************************************************
--
-- Title:
FIFO Using DPRAM
--
-- Created:
Wed Aug 30 14:54:17 2000
-- Author: DEEPAK GEORGE
-- Source File Name: fifo2.vhd
--
-- $Id: fifo2.vhd,v 1.1 2000/08/30 14:54:17
acts Exp $
--
-- Description: This is the code for a FIFO Using a DPRAM , bugs fixed and code
optimized.
--
--
-- Revision History: Rev 2.0 Optimized
--
-- $Log: fifo2.vhd,v $
--
--
************************************************************************
library
IEEE, STD;
use
IEEE.std_logic_1164.all;
use
IEEE.std_logic_components.all;
use
IEEE.std_logic_arith.all;
use
IEEE.std_logic_misc.all;
use
IEEE.std_logic_unsigned.all;
entity
fifo is
port
(clk : in std_logic;--CLOCK
rst : in
std_logic;--Reset
rd : in
std_logic;-- RD Active L
wr : in
std_logic;-- WR Active L
data1 : inout std_logic_vector(7 downto 0);--Data WR
data2 : inout std_logic_vector(7 downto 0);--Data RD
full : out
std_logic;-- FIFO FULL
p_full : out
std_logic;-- FIFO Partially
Full(>240)
p_epty :
out std_logic;-- FIFO Partially Empty(<15)
epty : out
std_logic -- FIFO EMPTY
);
end
fifo;
architecture
fifo_A of fifo is
component dpram
port
(clk : in std_logic; -- Clock
addr1 : in
std_logic_vector (7 downto 0); -- Address1
addr2 : in
std_logic_vector (7 downto 0); -- Address2
data1 : inout std_logic_vector(7 downto 0); -- Data
Port1
data2 : inout std_logic_vector(7 downto 0); -- Data Port2
rd_b : in
std_logic;
--Read0
wr_b : in
std_logic --Write0
);
end component;
signal W_add : std_logic_vector(7 downto 0);-- Write Addr Gen
signal R_add : std_logic_vector(7 downto 0);-- Read Addr Gen
signal C_add : std_logic_vector(7 downto 0);-- Check Count
signal wri : std_logic;
-- Internal Write Enable
signal rdi : std_logic;
-- Internal Read Enable
signal fulli : std_logic;
signal p_fulli : std_logic;
signal p_eptyi : std_logic;
signal eptyi : std_logic;
begin
U1
: port map dpram(clk => clk,
addr1=> w_add,
addr2=> r_add,
data1=> data1,
data2=> data2,
rd_b => rdi,
wr_b => wri
);
-- Write Enable on getting a WR input and if
FIFO is not full
wri <= '0' when (wr = '0' and fulli = '0')
else '1';
-- Read Enable on getting a RD input and if
FIFO is not empty
rdi <= '0' when (rd = '0' and eptyi = '0')
else '1';
---------------------------------------------------------------------------
-- Issue FIFO Status Signals
---------------------------------------------------------------------------
fulli <= '1' when (c_add =
"11111111") else '0';-- Full
if C_add= 255
eptyi <= '1' when (c_add =
"00000000") else '0';--
Empty if C_add = 0
p_eptyi
<= '1' when (c_add (7 downto 4) = "0000" and eptyi = '0') else
'0';-- Part full if C_add<15
p_fulli
<= '1' when (c_add (7 downto 5) = "111" and full = '0' ) else '0';-- Part Empty ifC_add>224
---------------------------------------------------------------------------
-- Genrate Write and Read Address
---------------------------------------------------------------------------
main
: process(clk,rst)
begin
if ( rst = '1') then
w_add
<= (others => '0');
r_add
<= (others => '0');
c_add
<= (others => '0');
elsif (clk'event and clk = '1') then
-------------------------------------------------------------------------
--
FIFO write , when w_add is 255 and if full = 0 then the writing will
--
start from 0 addr location again.
-------------------------------------------------------------------------
if (wri = '0') then -- FIFO Write Operation
w_add <= w_add + 1;
if (rdi = '0') then
c_add <= c_add;
else
c_add <= c_add + 1;
end if;
end if;
if (rdi = '0') then -- FIFO Read Operation
r_add <= r_add +1;
if (wri <= '0') then
c_add <= c_add;
else
c_add <= c_add -1;
end if;
end if;
end
process;
full <= fulli;
epty <= eptyi;
p_full<=
p_fulli;
p_epty<=
p_epty;
end
fifo_A;
END
OF FIFO OPTIMIZED
--
************************************************************************
-- - H/W Development Group
-- ************************************************************************
--
-- Title:
Dual Port RAM 256*8
--
-- Created:
Mon Aug 28 13:21:25 2000
-- Author:
DEEPAK GEORGE
-- Source File Name: dpram.vhd
--
-- $Id: dpram.vhd,v 1.1 2000/08/28 13:21:25
acts Exp $
--
-- Description: This file gives the code for a
dual port DPRAM "addr1" and
-- "data1" is used to
write data and "addr2" and "data2" is used
-- to read the data from the
RAM.
--
-- Revision History:
--
-- $Log: dpram.vhd,v $
--
--
************************************************************************
library
IEEE, STD;
use
IEEE.std_logic_1164.all;
use
IEEE.std_logic_components.all;
use
IEEE.std_logic_arith.all;
use
IEEE.std_logic_misc.all;
use
IEEE.std_logic_unsigned.all;
entity
dpram is
port
(clk : in std_logic; -- Clock
addr1 : in
std_logic_vector (7 downto 0); -- Address1
addr2 : in
std_logic_vector (7 downto 0); -- Address2
data1 : inout std_logic_vector(7 downto 0); -- Data
Port1
data2 : inout std_logic_vector(7 downto 0); -- Data Port2
rd_b : in
std_logic; -- Read
wr_b : in
std_logic --
Write
);
end
dpram;
architecture
dpram_A of dpram is
type
ram_array is array (0 to 255 ) of std_logic_vector(7 downto 0);
signal
ram : ram_array;
begin
---------------------------------------------------------------------------
-- Write Process : Data is writen into the
DPRAM with an active low wr_b
-- signal. The address is received from the
addr1 bus and the data from
-- the data1 bus.(PORT 1)
---------------------------------------------------------------------------
write
: process(clk)
begin
if (clk'event and clk = '1') then
if (wr_b='0') then
ram(addr1)<= data1;
end if;
end if;
end
process;
---------------------------------------------------------------------------
-- Read Process : Data is read from the DPRAM
with an active low rd_b
-- signal. The address is obtained fromthe
addr2 bus and the data is
-- outputed to the data2 bus (PORT 2)
---------------------------------------------------------------------------
read
: process (clk)
begin
if (clk'event and clk = '1') then
if (rd_b = '0') then
data2<= ram(addr2);
else
data2<=(others=>'Z');
end if;
end if;
end
process;
end
dpram_A;
END
OF DPRAM
In this code a FIFO has been implemented using a DPRAM , its has
indications for FULL , Partially FULL, EMPTY and Partially Empty conditions .