-- ************************************************************************

-- Copyright (C) 1994 - Centre for Development of Advanced Computing

-- - H/W Development Group

-- ************************************************************************

--

-- Title: Single Port RAM 16*1

--

-- Created: Mon Aug 28 13:06:27 2000

-- Author: DEEPAK GEORGE

-- Source File Name: spram.vhd

--

-- $Id: spram.vhd,v 1.1 2000/08/28 13:06:27 acts Exp $

--

-- Description: This is a vhdl code for a single port RAM 16*1 with the

-- RAM block instanced on chip. Sync write, Asyn Read. This will -- instantiate a RAM block from a Xilinx CLB.

--

-- Revision History:

--

-- $Log: spram.vhd,v $

--

-- ************************************************************************

library IEEE, STD;

use IEEE.std_logic_1164.all;

use IEEE.std_logic_components.all;

use IEEE.std_logic_arith.all;

use IEEE.std_logic_misc.all;

use IEEE.std_logic_unsigned.all;

entity spram is

port (clk : in std_logic; -- Clock

rst : in std_logic; -- Reset

rd : in std_logic; -- Read

wr : in std_logic; -- Write

addr : in std_logic_vector(3 downto 0); -- Address

data : inout std_logic -- Data

);

end spram;

architecture spram_A of spram is

type ram_array is array (0 to 15 ) of std_logic;

signal Ram : ram_array;

begin

main : process(clk,rst,rd,addr,ram)

begin

if (clk'event and clk = '1') then

if (wr = '1' ) then -- Read from RAM

Ram(conv_integer(addr)) <= data;

end if;

end if;

if (rd = '1') then -- Write to RAM

data <= ram(conv_integer(addr));

else

data <= 'Z';

end if;

end process;

end spram_A;