Computer Aided Design(CAD) of digital of
systems2002-2003 First semister.
I ,(gopikrishna pinninti) had done this course under
Prof.M.Balakrishnan .
Have the fun with these assignments.
1.Assignment 1
2.Assignment 2
3.Assignment 3
Assignment1 Description
In VHDL describe/design the following:
1-bit full adder (dataflow or structural).
1-digit BCD adder (structurally from above).
Assume the two BCD inputs are coming serially (at the rate of 1 bit/clock cycle), design a FSM for converthing this serial input to parallel 1-digit BCD.
Structurally compose two instantiations of the serial-to-parallel BCD
converter and one BCD adder. Write a test bench and show addition of
the following sequence of inputs "0010 0011 0110" and "0010 0110 0001"
(i.e. 236 and 261) digit by digit.
Assignment2 Description
Write a non-pipelined cycle accurate sequential (process) VHDL description of one of the following three processors:
8085
Basic computer from Mano's book
MIPS from Hennessey & Patterson's book
Your description should contain the following:
Clearly indicate the parts which handle fetch, decode and execute.
Enough instructions to implement a bubble sort algorithm
Testbench containing the memory which is initialized with the bubble sort program for sorting 16 numbers and 16 data values in proper location.
Convert your design into a pipelined design with three processes,
fetch, decode and execute. Create an instruction buffer for handling
variable execution time.
I simulated 8085 microprocessor both non-pipelining and pipeling.
code in tar file format
Assignment3 Description
Implement any of the algorithms related to behavioural synthesis, logic synthesis, state assignment, retiming, technology mapping.
You are encouraged to use public domain packages on ILP, BDD, any graph algorithm etc. you require for this purpose (in any programing language).
code in C
Web links
VHDL cookbook by Peter J. Ashenden,
University of Adelaide South Australia © 1990, Peter J. Ashenden.
BDD tutorial
Embedded @ IITD
Gopikrishna