Mark C. Lee: Resume

Mark C. Lee

mclee@alum.mit.edu

Seeking a challenging position in chip design. 8 years of industry experience from logic design to tapeout, with most recent work in areas of physical chip integration and timing closure. Well organized, excellent communication skills, and a self-motivated. Able to manage and execute on complex projects. Has both technical and management experience building flows and teams. Varying proficiency with tools from Synopsys and Cadence, perl, C, and a variety of EDA file formats (verilog, sdc, lef/def, .lib).

Experience
4/00 - ATI Technologies Inc. - PC Business Unit - Desktop Engineering Santa Clara, CA

6/06- Integration Manager
Responsible for the flow from RTL Synthesis to Physical Design Place-and-Route Start, including hierarchical netlisting, synthesis, chip floorplanning, toplevel budgeting, IP management, and netlist quality. Flow required to support multiple projects across multiple geographic locations simultaneously.

11/05-6/06 Physical Integration and Timing Closure Manager
Built and managed a team of 8 for Physical Integration and Full Chip Timing Closure for ATI's next generation flagship desktop graphics chip. Physical Integration includes chip floorplanning, block sizing and pin assignments, timing budgeting, netlist quality checks, and IP integration and management. Full Chip Timing Closure challenges include constraint management, STA flow and execution, SI validation, capacity/runtime issues, and hierarchical design complications. Owned technical management, flow and schedule ownership and execution, employee training and development, and some technical duties.

11/03-11/04 Physical Design CAD Manager
Owned project CAD support and future CAD initiatives

11/02-11/03 Physical Design Manager
Managed entire Physical Design Team of 20+ engineers from gates-to-gdsii for the Radeon X800 (Pro/XT/XT-PE) product manufactured using a TSMC 0.13um process technology with 160M+ transistors. Owned technical management, project schedule ownership and execution, flow development and execution, and had some technical duties. Design space included chip and block level floorplanning, timing budgeting, placement, CTS, routing, physical optimization, and various timing and physical validation. Interfaced with foundry for tapeout and silicon validation activities, resulting in first silicon production.

4/02-11/02 Staff Engineer
Owned Physical Design duties for the Textures Block for the Radeon 9600 product manufactured using TSMC 0.13um process with 75M+ transistors. Executed block level floorplanning, placement, CTS, routing, physical optimnization, and timing and physical validation. Owned flow development and support for hiVt cell swapping to improve leakage power throughout the chip.

4/00-4/02 Senior Engineer
Owned Front End Netlist Integration and Full Chip Timing for the Radeon 9700 product using TSMC 0.15um process with 110M+ transitors. Owned flow development and execution for both activities.

8/99-4/00 Artx, Inc. - Member of Technical Staff Palo Alto, CA
Owned the Audio Interface (AI) for Nintendo Gamecube's GPU Flipper using NEC 0.18um process with 51M+ transistors. Using a given design spec, owned logic design and verification of the AI. Verification included block level verilog testbenches, C model, chip level verification support, and post-silicon lab work. Also owned chip level gate level simulations for Flipper.

9/98-8/99 sgi - Member of Technical Staff, Advanced Graphics Division Mountain View, CA
Contributed to Raster Chip verification on the Bali Project, a next generation high end graphics system. Duties included writing block level tests and C models.

Education
Massachusetts Institute of Technology Cambridge, MA
1993-1997 Master's of Engineering in Electrical Enginerring and Computer Science
1997-1998 Bachelor's of Science in Electrical Engineering.

Misc
US Citizen, verbally fluent in Mandarin Chinese

References Available Upon Request


	Seeking a challenging position in chip design. 8 years of industry experience from logic design to tapeout, with most recent work in areas of physical chip integration and timing closure. Well organized, excellent communication skills, and a self-motivated. Able to manage and execute on complex projects. Has both technical and management experience building flows and teams. Varying proficiency with tools from Synopsys and Cadence, perl, C, and a variety of EDA file formats (verilog, sdc, lef/def, .lib).


Experience
4/00 -	ATI Technologies Inc. - PC Business Unit - Desktop Engineering	Santa Clara, CA


6/06-	Integration Manager
	Responsible for the flow from RTL Synthesis to Physical Design Place-and-Route Start, including hierarchical netlisting, synthesis, chip floorplanning, toplevel budgeting, IP management, and netlist quality. Flow required to support multiple projects across multiple geographic locations simultaneously.

11/05-6/06	Physical Integration and Timing Closure Manager
	Built and managed a team of 8 for Physical Integration and Full Chip Timing Closure for ATI's next generation flagship desktop graphics chip. Physical Integration includes chip floorplanning, block sizing and pin assignments, timing budgeting, netlist quality checks, and IP integration and management. Full Chip Timing Closure challenges include constraint management, STA flow and execution, SI validation, capacity/runtime issues, and hierarchical design complications. Owned technical management, flow and schedule ownership and execution, employee training and development, and some technical duties.

11/03-11/04	Physical Design CAD Manager
	Owned project CAD support and future CAD initiatives

11/02-11/03	Physical Design Manager
	Managed entire Physical Design Team of 20+ engineers from gates-to-gdsii for the Radeon X800 (Pro/XT/XT-PE) product manufactured using a TSMC 0.13um process technology with 160M+ transistors. Owned technical management, project schedule ownership and execution, flow development and execution, and had some technical duties. Design space included chip and block level floorplanning, timing budgeting, placement, CTS, routing, physical optimization, and various timing and physical validation. Interfaced with foundry for tapeout and silicon validation activities, resulting in first silicon production.

4/02-11/02	Staff Engineer
	Owned Physical Design duties for the Textures Block for the Radeon 9600 product manufactured using TSMC 0.13um process with 75M+ transistors. Executed block level floorplanning, placement, CTS, routing, physical optimnization, and timing and physical validation. Owned flow development and support for hiVt cell swapping to improve leakage power throughout the chip.

4/00-4/02	Senior Engineer
	Owned Front End Netlist Integration and Full Chip Timing for the Radeon 9700 product using TSMC 0.15um process with 110M+ transitors. Owned flow development and execution for both activities.



8/99-4/00	Artx, Inc. - Member of Technical Staff	Palo Alto, CA
	Owned the Audio Interface (AI) for Nintendo Gamecube's GPU Flipper using NEC 0.18um process with 51M+ transistors. Using a given design spec, owned logic design and verification of the AI. Verification included block level verilog testbenches, C model, chip level verification support, and post-silicon lab work. Also owned chip level gate level simulations for Flipper.


9/98-8/99	sgi - Member of Technical Staff, Advanced Graphics Division	Mountain View, CA
	Contributed to Raster Chip verification on the Bali Project, a next generation high end graphics system. Duties included writing block level tests and C models.


Education
	Massachusetts Institute of Technology	Cambridge, MA
1993-1997	Master's of Engineering in Electrical Enginerring and Computer Science
1997-1998	Bachelor's of Science in Electrical Engineering.


Misc
	US Citizen, verbally fluent in Mandarin Chinese
	References Available Upon Request