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Altera
Tony Balsamo
Contact:
tony_balsamo@bd.com
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References
BD Spec & Procedure Numbers
Design Process - DPPD 4041
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Functional Description - DPPD 4042
Design Specification - DPPD 4040
Verification Test Plan - DPPD 4039
Cypress
Xilinx
Design Data Sheet - SOP5242
Product Risk Management - SOP5285
Product Lifecycle - SOP5230
Quality manual - QM 10000
Design History Record - SOP6007
Prod Dev Process - SOP6011
Document Controls - SOP5300
Risk Analysis Procedure - SOP5291
Writing Test Protocol - DPPD4015
Writing Eval Report - DPPD4016
Configuration Mgmt - DPPD2109
Tech Review Proc - DPPD1001
Bidirectional Bus Example
Verilog Examples
Verilog Examples 2
HDL Reference
Verilog Examples 3
Verilog Examples 4
Bucknell Verilog Manual
Qualis Verilog Reference Sheet
Verilog Quick  Reference