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| FLASH (FLexible Architecture for SHared memory) FLASH is a single-address-space machine consisting of a large number of processing nodes connected by a low-latency, high-bandwidth interconnection network. Every node is identical containing a high-performance off-the-shelf microprocessor with its caches, a portion of the machine's distributed main memory, and the MAGIC (Memory And General Interconnect Controller) node controller chip. The MAGIC chip forms the heart of the node, integrating the memory controller, I/O controller, network interface, and a programmable protocol processor. This integration allows for low hardware overhead while supporting both cache-coherence and message-passing protocols in a scalable and cohesive fashion. The base cache-coherence protocol is directory-based and has two components: a scalable directory data structure, and a set of handlers. For a scalable directory structure, FLASH uses dynamic pointer allocation. Fundamentally, protocol handlers must perform two tasks: data movement and state manipulation. The MAGIC architecture exploits the relative independence of these tasks by separating control and data processing. As messages enter the MAGIC chip they are split into message headers and message data. Message headers flow through the control macropipeline while message data flows through the data transfer logic. Both message-passing and cache-coherence protocols require data connections among the network, local memory, and local processor. Because the structure of these connections is protocol-independent, the data transfer logic can be implemented completely in hardware without causing a loss of overall protocol processing flexibility. The hardwired implementation minimizes data access latency, maximizes data transfer bandwidth, and frees the protocol processor from having to perform data transfers itself. The control macropipeline must satisfy two potentially conflicting goals: it must provide flexible support for a variety of protocols, yet it must process protocol operations quickly enough to ensure that control processing time does not dominate the data transfer time. A programmable controller provides the flexibility. Additional hardware support ensures that the controller can process protocol operations efficiently. The goal is for FLASH to operate well both in a traditional supercomputer environment and in a general-purpose, multiprogrammed environment. The latter environment poses significant challenges since general-purpose environments typically contain large numbers of processes making many system calls and small I/O requests. In addition, users expect good interactive response, fair sharing of the hardware, protection against malicious programs, and extremely rare system crashes. The combination of workload characteristics and user requirements rules out using a standard supercomputer operating system for FLASH. Scalability and fault containment requirements rule out using a general-purpose operating system designed for small-scale shared-memory multiprocessors. To address these issues, a new operating system for FLASH, is being developed, called Hive. Beneath a standard shared-memory multiprocessor API, Hive organizes the hardware nodes into groups called cells. Each cell runs a semi-autonomous NUMA-aware operating system. The division into cells provides the replication needed for a highly-scalable operating system implementation and allows for fault containment. Cells interact as a distributed system internal to Hive, using the firewall and message-passing mechanisms of the MAGIC chip for fault isolation. The number of nodes per cell can be configured for different workload and availability requirements. Hive supports shared memory between applications on different cells, and can allocate processor and memory resources from multiple cells to a single application. This support allows flexible, fine-grained sharing of the machine by large and small applications, despite the fault containment partitions. |