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| The Fujitsu VPP5000 series. Machine type: Distributed-memory vector multi-processor Models: VX-E, VPP300-E, VPP5000-E Operating system: UXP/V (a V5.4 based variant of Unix) Connection structure: Full distributed crossbar Compilers: Fortran 90/VP (Fortran 90 Vector compiler), Fortran 90/VPP (Fortran 90 Vector Parallel compiler), C/VP (C Vector compiler), C, C++ Year of introduction: 1999 |
| Model VPP5000U VPP5000 Clock cycle 3.3 ns 3.3 ns Theor. peak performance Per proc. (64-bit) 9.6 Gflop/s 9.6 Gflop/s Maximal (64-bit) 9.6 Gflop/s 1.22 Tflop/s Main memory Memory/node <= 16 GB <= 16 GB Memory/maximal <= 16 GB <= 2 TB No. of processors 14-128 14-128 Memory bandwidth Memory banwidth/proc. 38.4 GB/s 38.4 GB/s Communication bandwidth Point-to-point --- 1.6 GB/s |
| The VPP5000 is the sucessor of the former VPP700/VPP700E systems (with E for extended, i.e., the clock cycle 6.6 instead of 7 ns). The overall architectural changes with respect to the VPP700 series are slight. The clock cycle has been halved and the \fp vectorpipes are able to deliver floating multiply-add results. With a replication factor of 16 for these vectorpipes, 32 floating-point results per clock cycle can be generated, at least in theory. In this way a four-fold increase in speed per processor can be attained with respect to the VPP700E. The architecture of the VPP5000 nodes is almost identical to that of the VPP700: Each node, called a Processing Element (PE) in the system is a powerful (9.6 Gflop/s peak speed with a 3.3 ns clock) vector processor in its own right. The vector processor is complemented by a RISC scalar processor with a peak speed of 1.2 Gflop/s. The scalar instruction format is 64 bits wide and may cause the execution of up to 4 operations in parallel. Each PE has a memory of up to 16 GB while a PE communicates with its fellow PEs at a point-to-point speed of 1.6 GB/s. This communication is taken care of by separate Data Transfer Units (DTUs). To enhance the communication efficiency, the DTU has various transfer modes like contiguous, stride, sub array, and indirect access. Also translation of logical to physical PE-ids and from Logical in-PE address to real address are handled by the DTUs. When synchronisation is required each PE can set its corresponding bit in the Synchronisation Register (SR). The value of the SR is broadcast to all PEs and synchronisation has occurred if the SR has all its bits set for the relevant PEs. This method is comparable to the use of synchronisation registers in shared-memory vector processors and much faster than synchronising via memory. The network is a direct crossbar which should lead to an excellent throughput of the network. This is in contrast to the VPP700 where a level-2 crossbar was employed for configurations larger than 16 processors. On special order 512 PE systems can be built by Fujitsu, quadrupling the maximum amount of memory and the theoretical peak performance. The VPP5000U is one of the few single-processor vector processors that is offered. It is simply a single-processor version of the VPP5000, of course without the network and data transfer extentions that are required in the VPP5000. The Fortran compiler that comes with the VPP5000 has extensions that enable data decomposition by compiler directives. This evades in many cases restructuring of the code. The directives are different from those as defined in the High Performance Fortran Proposal but it should be easy to adapt them. Furthermore, it is possible do define parallel regions, barriers, etc., via directives, while there are several intrinsic functions to enquire about the number of processors and to execute POST/WAIT commands. Furthermore, also a message passing programming style is possible by using the PVM or MPI communication libraries that are available. Measured Performances: The system was announced in November 1999 and some results are available by now. For a 32 processor system a speed of 296.1 Gflop/s was measured solving an order 170,880 full linear system which amounts to an efficiency of 96%. On a single processor a speed of 6.04 Gflop/s was measured in solving a system of order 2000. In evaluating a 10-th order polynomial a speed of 8.68 Gflop/s was observed, also an efficiency of over 90%. |
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