|I am currently a post graduate student in UTM, Malaysia|
|I am doing projects on VLSI, designing a shortest path hardware for computer networking application.
I am using some EDA tools, such as Synopsys DC, Altera MAX+Plus II, Tanner Tools, and some SPICE simulation program
I have the change to touch on VHDL bahavioral description design, synthesis, place and route, and SPICE simulation. Besides, I also developed and enhanced the cell library and synthesis technology library. A rapid design flow which enable VHDL to VLSI implementation had also been setup.
|1. Nasir Shaikh-Husin, Mohamad Khalil Hani and Teoh Giap Seng, "Implementation of Recurrent Neural Network Algorithm for Shortest Path Calculation in Network Routing", Proc of IEEE International Symposium on Parallel Architectures, Algorithms and Networks (ISPAN), Manila Philipines, 2002, pg 313-317. Download
2. Nasir Shaikh-Husin, Mohamad Khalil Hani and Teoh Giap Seng, "Design and Implementation of a Shortest Path Processor for Network Routing, Proc of the 2nd World Engineering Congress, Malaysia, July 2002, EE175-179. Download