This project "ATM CRC(Cyclic Redundancy Check) control" involves HEC (Header
Error Control) and verification of the correctness of OAM(Operations and Maintenance). In
our design, we use 6 modules to achieve project goal, including top module "CRC_OAM"
and 5 parallel submodules. "FSM" module controls state function, "Cell counter" module
counts cells number, "Byte counter" module counts 53 bytes of each cell, "CRC8" module
checks header and "CRC10" module checks OAM payload. All of modules are designed by
verilog codes. Input data of CRC8 and CRC10 are also tested  by C++ code to verify the
correctness results from verilog files. Finally design is also verfied by synthesis and synopsys.

FSM Module

Module name  -- ATM_Cell_Controller
Input:
clock  -- System global clock.
reset       -- System global reset.
check       -- Input from "ATM_Cell_Controller" module,   indicate CRC8 remainder result
( high: not valid      header, low valid header).
count_cell  -- Input from "COUNT_CELL" module, indicate  increment of valid or invalid cell numbers,
reset number when opposite type cell comes in.
count_byte  -- Input from "COUNT_BYTE" module, starts counting
every 53 bytes of a cell in presync and sync states.
OAM_CELL    -- Input from "Reminder" module, indicate if it is  OAM cell.

Output:
bit_correction -- Indicate single bit error occurs and needs to
be corrected in presync and sync states,  correction mode.
cd_state       -- Indicate current state.
0 - hunt state, 1 - presync state,  2 - sync state,  3 - invalid state.
count_start    -- Indicate the current header is valid and start counting cell and byte numbers.
count_clear -- Indicate the following header is invalid and reset cell and byte numbers.
data_valid -- Indicate the output data is valid or invalid.
switch_2_invalid -- Clear counter to 0 if header type changes.
second  -- Indicate the current header is invalid.
second_time -- Indicate the current header is second consecutive invalid header.

Module function description: Module starts from hunt state and all output data are
invalid. As soon as a valid header is found, state changes to
presync. In presync state, cells are counted. If 6 valid headersare found (this could includes
non consecutive single bit error headers), state changes to sync state. But if two
consecutiveinvalid headers are found, state jumps back to hunt. Otherwise,state stays
in presync. In sync state, only 7 consecutive invalid headers can change state to hunt.
Otherwise, state will stay insync. Under any circumstance, two consecutive invalid
headers are found, output data are invalid. And when OAM cell is found,
regular cell data output should be high impedance.

CRC8 Module

Module name  -- Reminder
Input:
clock  -- System global clock.
DataIn  -- Data input.
bit_correction -- Input from "CRC_FSM" module, indicate single
bit error occurs and needs to be corrected in presync and sync states, correction mode.
count_clear -- Input from "CRC_FSM" module, indicate the following
header is invalid and reset cell and byte numbers.
count_cell -- Input from "CRC_FSM" module, indicate the following header is
invalid and reset cell and byte numbers.

Output:
check  -- Indicate CRC8 remainder result( high: not valid header, low:valid header).
out   -- Temporary register to store output data.
data_out  -- Data output.
OAM_check  -- Indicate if the first three bytes of a valid cell header is all 0.
OAM_CELL  -- Indicate if it is OAM cell.
Module function description: We use long division method 5 header bytes(40 bits) to
divide by crc8 polynomial x^8 + x^2 + x + 1, which is 100000111.
The remainder 8 bits will generate a pattern in terms of dividend
40 bits variables. However, each remainder bit will have a long
exclusive OR operation, up to more than 20 bits. Therefore, we
create 4 temporary registers to store those XOR operation in
order to use it next time. Finally we XOR these four temporary
registers with constant value 55 hexadecimal numbers. The result
is desire remainder. Do NOR operation of each remainder bit to
see if the result is 0. Yes, then it is a valid header. No, it is
a invalid header. Then shift first byte out to data output, shift
each byte forward and get next data input byte. Second part of
this module is one bit correction. In presync and sync states,
when one bit error occurs, bit correction signal becomes high and
we use correction look up table to correct the error. Since only
one single bit is allowed, we can expect the correction look up
table array is 40.

CRC10 Module

Module name  -- CRC_10_CHECK
Input:
clock  -- System global clock.
out   -- Input from "Reminder" module, temporary  register to store output data.
OAM_CELL  -- Input from "Reminder" module, indicate if it is OAM cell.
count_byte -- Input from "COUNT_BYTE" module, starts counting every 53
bytes of a cell in presync and sync states.
Output:
OAM_valid  -- Indicate if the OAM payload is valid after      doing CRC10 operation.
OAM_data  -- Output OAM data.
Module description: As soon as OAM_CELL indicates the coming cell is OAM, this
module will do crc10 operation to check payload. The crc10
polynomial is x^9 + x^8 + x^6 + x^4 + x^2 + 1, which is
1101010101. Since we can't use the whole 48 bytes of payload to
divide by polynomial, we use recursive method to do long
division. We create 3 registers to store data input stream. The
first two bytes is dividend pattern and this division will create
10 bits remainder, which means we can use this remainder to put
back first byte of dividend pattern and get the next byte of
input data to be the second byte of dividend pattern and keep
doing division operation. But since the last two bits of
remainder will affect second byte dividend pattern, we need to
change first two bits of next input byte. Keep doing recursive
operation until last two bytes of payload. At this time, we need
to change our remainder pattern so that no more last two bits
will come from next byte. Do NOR operation of last remainder and
see the result is 0. Yes, OAM cell is valid. NO, OAM cell is
invalid.

Cell Counter Module

Module name  -- COUNT_CELL
Input:
clock   -- System global clock.
count_byte  -- Input from "COUNT_BYTE" module, starts counting every 53 bytes of a cell in
presync and sync states.
one_cell   -- Input from "COUNT_BYTE" module, indicate one complete cell.
count_clear  -- Input from "CRC_FSM" module, indicate the following header is invalid and reset cell and byte numbers.
switch_2_invalid  -- Input from "ATM_Cell_Controller" module. Clear counter to 0 if header type changes.
cd_state   -- Input from "ATM_Cell_Controller" module. Indicate current state.
0 - hunt state,
1 - presync state,
2 - sync state,
3 - invalid state.
bit_correction  -- Input from "CRC_FSM" module, indicate single bit error occurs and needs to be
corrected in presync and sync states, correction mode.
OAM_CELL   -- Input from "Reminder" module, indicate if it is OAM cell.
Output:
count_cell  -- Indicate the following header is invalid and reset cell and byte numbers.
first_byte  -- Indicate the first byte of a cell.
Module description: The major part of this module is counting cells. When header
types change, e.g. from valid header to invalid and vice versa,
cell counting will reset. We use this function to do delta and
alpha accumulation. The second part of this module is output
"first byte". When a complete cell passed, first byte will
generate a clock cycle high on the next clock cycle, if the state
doesn't change to hunt state.

Byte Counter Module

Module name -- COUNT_BYTE
Input:
clock  -- System global clock.
count_clear -- Input from "CRC_FSM" module, indicate the following header is invalid and reset cell and
byte numbers.
count_start -- Input from "CRC_FSM" module, indicate the following header is invalid and reset cell and
 byte numbers.

Output:
one_cell  -- Indicate one complete cell.
count_byte -- Output current byte number.
Module description: This only function of this module is counting 53 bytes for a
complete cell. If cell boundary is found, start counting bytes
from 0. In hunt state, byte counter doesn't work.

ATM CRC Module

Module name -- CRC_OAM
Input:
clock  -- System global clock.
reset  -- System global reset.
DataIn  -- Data input.
Output:
data_out  -- Data output.
data_valid -- Indicate the output data is valid or invalid.
first_byte -- Indicate the first byte of a cell.
cd_state  -- Indicate current state.
0 - hunt state,      1 - presync state, 2 - sync state,    3 - invalid state.
OAM_data  -- Output OAM data.
OAM_valid  -- Indicate if the OAM payload is valid after doing CRC10 operation.

Module description: This is the top module of all submodules. The major function
of this module is coordinate those submodules.