/*module************************************
*
* NAME:  CRC_test_fixture
*
* DESCRIPTION: test fixture for the all modules
*
*
* NOTES:
*
* REVISION HISTORY
*    Date     Programmer    Description
*    4/11/99  Kuan-Chih Chen & Zhen Han
*
*M*/

/*=================== Context =============================*/
`include "CRCoAM.v"

/*=================== Declarations ========================*/
module CRC_test_fixture;

/*---------------- Registers----------------*/
reg clock, reset;
reg [1:8] DataIn;
reg [1:8]dat[1:7950]; /*create 5564 register for input data */

/*---------------- Integers ----------------*/
integer j;

/*----------------  Nets ----------------*/
wire check;
wire bit_correction;
wire [1:0] cd_state;
wire count_start,data_valid;
wire [7:0] count_cell;
wire count_clear;
wire first_byte;
wire [5:0] count_byte;
tri [1:8] data_out,OAM_data;
wire OAM_valid;
wire second;
wire second_time;
wire OAM_check;
/*=================== Initialization ========================*/
initial
begin
      $shm_open("crcEight.shm");
      $shm_probe("AS");
      $display("Testing CRC \n");
      $monitor("time = %d; clock = %b; data_out=%h; OAM_out=%h; cd_state=%d; data_valid=%b; OAM_valid=%b",
      $stime, clock, data_out,OAM_data, cd_state, data_valid, OAM_valid);
      clock = 0;
      reset = 1;
      #1 reset = 0;
      #3 reset = 1;

      $readmemh("/ncsu/ece520_info/hw/CRCprojCompliance/COMPLIANCE2/compliance2.txt",dat,1,7950);
  for (j=1;j<7950;j=j+1)
                   #2 DataIn = dat[j];

                $shm_close();
                $finish;

      #20 $shm_close();
      $finish;
 end
 always #1 clock=~clock; /* 2ns clock cycle */

 CRC_OAM u1(clock,reset,DataIn,check,bit_correction,cd_state,count_start,data_valid,count_cell,count_clear,first_byte,count_byte,data_out,OAM_valid,OAM_data,second,second_time,OAM_check);

endmodule /* CRC_test_fixture */

/*=================== Declarations ========================*/
module
CRC_OAM(clock,reset,DataIn,check,bit_correction,cd_state,count_start,data_valid,count_cell,count_clear,first_byte,count_byte,data_out,OAM_valid,OAM_data,second,
second_time, OAM_check);

/*-----------  Inputs--------------------------------*/
input  clock;   /* clock */
input  reset;   /* globe reset output and registers */
input  [1:8] DataIn;  /* Data input */

/*-----------  Outputs--------------------------------*/
output  check;   /* indicate if header is error */
output  bit_correction; /* indicate bit error needs to be corrected  */
output  [1:0] cd_state; /* indicate the current state */
output  count_start;  /* indicate start counting bytes if cell boundry is found*/
output data_valid;   /* indicate output data is valid */
output  [7:0] count_cell; /* count cell numbers */
output  count_clear;  /* reset counter number to zero */
output first_byte;   /* indicate the first byte of a cell */
output  [5:0] count_byte; /* count every 53 bytes */
output  [1:8] data_out; /* data output */
output [1:8] OAM_data; /* OAM data output */
output  OAM_valid; /* indicate if OAM cell is valid */
output second;  /* header is wrong consecutive second time */
output second_time; /* header is wrong consecutive second time */
output  OAM_check; /* check OAM */
/*---------------- Registers----------------*/
wire [7:0] count_cell;
wire [1:0] cd_state;
wire [5:0] count_byte;
wire count_clear,first_byte,count_start,check,bit_correction;
wire switch_2_invalid, one_cell;
wire OAM_CELL;   /* coming cell is OAM cell */
wire [1:8] out;   /* output from CRC8 */
 

/*---------------- Submodules ----------------*/
/* FSM module -- do control state function */
/* Counter module -- do counter cells function */
/* Counter byte module -- count 48 bytes function */
/* CRC8 module -- do crc8 checking function */
/* CRC8 module -- do crc10 checking function */

ATM_Cell_Controller
u2(clock,reset,check,count_cell,count_byte,OAM_CELL,bit_correction,cd_state,count_start,count_clear,data_valid,switch_2_invalid,second,
second_time);
COUNT_CELL u3(clock,count_byte,one_cell,count_clear,switch_2_invalid,cd_state,bit_correction,OAM_CELL,count_cell,first_byte);
COUNT_BYTE u4(clock,count_clear,count_start,one_cell,count_byte);
Reminder u5(clock,DataIn,bit_correction,count_clear,one_cell,check,out,data_out,OAM_Check,OAM_CELL);
CRC_10_CHECK u6(clock,out,OAM_CELL,count_byte,OAM_valid,OAM_data);
 

endmodule /* CRC_OAM */

/*-----------Inputs--------------------------------*/

input clock;   /* clock */
input  reset;   /* globe reset output and registers, cd_state go back "hunt" */
input  check;   /* check remainder  */
input  [7:0] count_cell; /* accumulate delta value */
input  [5:0] count_byte; /* count increment bytes */
input  OAM_CELL;  /* indicate coming cell is OAM cell */

/*-----------Outputs--------------------------------*/

output  bit_correction; /* indicate header has error and needed to be corrected */
output  [1:0] cd_state; /* indicate current state */
output count_start;   /* inform counter to count now */
output count_clear;  /* reset counter number to zero */
output data_valid;   /* indicate output data is valid */
output  switch_2_invalid; /* switch to detection mode */
output  second;
output  second_time;

parameter [1:0]  /* synopsys enum state */
 hunt = 2'b00,
 presync = 2'b01,
  sync = 2'b10,
 invalid_output = 2'b11;

/*----------------Nets and Registers----------------*/

reg [1:0] /*synopsys enum state*/  next_state,cd_state;
   /*synopsys state_vector cd_state*/

reg count_start, count_clear, bit_correction, switch_2_invalid;
reg data_valid;

//reg countSecond;
reg second;
reg second_time;
/*================ Operations ======================*/

always@(posedge clock or negedge reset)
 if(!reset)  cd_state <=hunt;
 else cd_state <= next_state;
 

always@(cd_state or check or count_cell or count_byte)
   begin
     bit_correction = 0; count_clear=0; count_start=1; switch_2_invalid=0; //second = 0;

 case (cd_state)  //synopsys full_case parallel_case
 hunt: begin
       count_clear=1; count_start=0;
        if(!check) /* check is low when cell boundry is found */
        begin
  next_state <= presync;
        end
        else next_state <= hunt;
       end
 presync: begin /* In presync state, start counting cells and bytes */
        count_start=1;
        if(count_byte==52) /* check if the last byte of the cell */
        begin
          if(count_cell==5) /* check if delta is 6 times already */
     next_state<=sync;
   else
    begin
          next_state<=presync;
     if(!check)
      second=0; /* no error on header */
     else
      begin
       if(second_time) /* error occurs consecutive twice */
        begin
         next_state<= hunt;
         count_clear = 1;
        end
       else /* 1 bit error occurs on error correction mode */
        begin
         second=1;
         next_state<=presync;
         bit_correction=1; /* bit error needs to be corrected */
           end
      end
    end
        end
       else next_state<=presync;
    end

 sync: begin
       if(count_byte==52) /* check if the last byte of the cell */
        begin
         if(check) /* error occurs */
                  begin
     bit_correction=1; /* bit error needs to be corrected */
     next_state <= invalid_output;
          switch_2_invalid=1; /* switch_2_invalid = 1, clear counter to 0 */
                  end
  else  next_state <= sync;
        end
       else
        next_state<=sync;
          end
 

 /* in this state, bit error needs not to be corrected */
 invalid_output: begin /* wrong header occurs */

   if(count_byte==52) /* check if the last byte of the cell */
            begin
            if(check) /* error occurs */
     begin
      if(count_cell == 5) /* alpha happens consecutive 7 times */
        begin
         next_state <= hunt;
         count_clear = 1;
        end
       else
         next_state <= invalid_output;
      end
        else /* no error occurs */
      begin
         next_state<=sync;
         switch_2_invalid=1; /* switch_2_invalid = 1, clear counter to 0 */
      end
      end
   else
        next_state<=invalid_output;

    end
   endcase
 end
 

 always@(cd_state or OAM_CELL or count_cell)
  begin
   if(!OAM_CELL) /* not OAM cell */
     begin
      if(cd_state==2'b00) /* hunt state */
       data_valid=0;
      else
       begin
         if(cd_state==2'b11) /* invalid_out state */
     begin
         if(count_cell==0)
           data_valid=1;
        else
     data_valid=0;
     end
  else
    data_valid=1;
 end
      end

    else
        data_valid=0;
  end

 always@(posedge clock)
  second_time= (cd_state==2'b01) ? second : 0;
 endmodule /* ATM_Cell_Controller */

/*module************************************
*
* NAME: COUNT_BYTE
*
* DESCRIPTION: count bytes
*
*
* NOTES:
*
* REVISION HISTORY
*    Date     Programmer    Description
*    4/11/99  Kuan-Chih Chen & Zhen Han
*
*M*/

/*=================== Declarations ========================*/
module COUNT_BYTE (clock,count_clear,count_start,one_cell,count_byte);

/*---------------  Inputs--------------------*/
input clock;  /* clock */
input count_clear; /* reset counter number to zero */
input count_start; /* indicate start counting bytes if cell boundry is found*/

/*---------------  Outputs-------------------*/
output one_cell; /* one complete cell */
output [5:0] count_byte; /* count every 53 bytes */

/*---------------- Registers-----------------*/
reg [5:0] count_byte;
reg one_cell;

/*---------------- Nets ---------------------*/
wire [5:0] next_count;

/*==================== Operations ======================*/
/* if cell boundary is found, start counting bytes from 00 */
always@(posedge clock)
   begin
   if(count_start)
   count_byte<=next_count;
   else count_byte<=0;
   end
/* one_cell is high on the last byte of a cell */
always@(posedge clock)
   one_cell<=(count_byte==51) ? 1 : 0;

assign next_count=(!count_start || count_clear || one_cell) ? 0 : (count_byte+1);

endmodule /* COUNT_BYTE  */

/*=================== Declarations ========================*/
module COUNT_CELL (clock,count_byte,one_cell,count_clear,switch_2_invalid,cd_state,bit_correction,OAM_CELL,count_cell,first_byte);

/*---------------  Inputs--------------------*/
input clock;  /* clock */
input [5:0] count_byte; /* count every 53 bytes */
input one_cell;  /* one complete cell */
input count_clear; /* reset counter number to zero */
input switch_2_invalid; /* indicate correction or detection mode */
input [1:0] cd_state; /* indicate the current state */
input bit_correction; /* indicate bit error needs to be corrected  */
input OAM_CELL;  /* coming cell is OAM cell */

/*---------------  Outputs-------------------*/
output [7:0] count_cell;/* count cell numbers */
output first_byte; /* indicate the first byte of a cell */

/*---------------- Registers-----------------*/
reg [7:0] count_cell;
reg first_byte;

/*---------------- Nets ---------------------*/
wire [7:0] next_c_cell;

/*==================== Operations ======================*/
/* "first byte" output is high only current state is not "hunt", not OAM cell */
/* and count byte just reset */
always@(OAM_CELL or cd_state or count_byte)
  begin first_byte=0;
  if(!OAM_CELL && cd_state!=2'b00 && count_byte==0)
    first_byte=1;
  else first_byte=0;
 end

/* reset count cell when error occurs, e.g. in detection mode or hunt state */
always@(posedge clock)
 begin
 if(!count_clear && !switch_2_invalid)
  count_cell<=next_c_cell;
 else count_cell<=0;
 end

assign next_c_cell = (!count_clear && one_cell ) ? (count_cell+1) : count_cell;

 endmodule /* COUNT_CELL */

/*module************************************
*
* NAME:  CRC_10_CHECK
*
* DESCRIPTION: do CRC10 to check OAM payload
*
*
* NOTES:
*
* REVISION HISTORY
*    Date     Programmer    Description
*    4/11/99  Kuan-Chih Chen & Zhen Han
*
*M*/

/*=================== Declarations ========================*/
module CRC_10_CHECK (clock,out,OAM_CELL,count_byte,OAM_valid,OAM_data);

/*---------------  Inputs--------------------*/
input clock;  /* clock */
input  [1:8] out; /* CRC8 output */
input  OAM_CELL; /* indicate it's OAM cell */
input  [5:0] count_byte; /* count every 53 bytes */

/*---------------  Outputs-------------------*/
output OAM_valid; /* indicate if OAM cell is valid */
output [1:8] OAM_data; /* OAM data output */

/*---------------- Registers-----------------*/
reg [1:8] g,h,i; /* 3 input data registers */
reg [1:8] crc10; /* 1st temp store remainder result */
reg [1:7] lastCRC; /* last remainder byte */
reg OAM_valid, OAM_CRC, OAM_CRC2,OAM_CRC3;
reg [1:8] CRC10_2; /* 2nd temp store remainder result */

/*---------------- Nets ---------------------*/
wire [1:8] k;
wire [1:2] g2,g3;
tri [1:8] OAM_data;

/*==================== Operations ======================*/
/* use recursive method to do long division, here is the remainder pattern */
always@( posedge clock)
begin
    if(OAM_CRC2)
    begin
      crc10[1]<=k[5]^k[6]^k[7]^k[8]^g3[1];
      crc10[2]<=k[1]^k[5]^g3[2];
      crc10[3]<=k[1]^k[2]^k[6]^g[3];
      crc10[4]<=k[2]^k[3]^k[7]^g[4];
      crc10[5]<=k[3]^k[4]^k[8]^g[5];
      crc10[6]<=k[4]^k[6]^k[7]^k[8]^g[6];
      crc10[7]<=k[1]^k[6]^g[7];
      crc10[8]<=k[2]^k[7]^g[8];

/* last remainder pattern */
      lastCRC[1]<=k[3]^k[4]^k[5]^k[6]^k[7];
      lastCRC[2]<=k[3]^k[8];
      lastCRC[3]<=k[4]^g3[1];
      lastCRC[4]<=k[2]^k[4]^k[5]^k[6]^g[4];
      lastCRC[5]<=k[4]^g[5];
      lastCRC[6]<=k[5]^g[6];
      lastCRC[7]<=k[2]^k[3]^k[4]^k[5]^k[6]^k[7];
 

    end
    else
     begin
      crc10<=0;
      lastCRC<=0;
     end
  end

/* OAM cell is valid only final remainder is 0 */
always@(OAM_CRC or count_byte or lastCRC)
  begin
   if(OAM_CRC)
     begin
       if(count_byte==1)
         OAM_valid=~|lastCRC;
       else
         OAM_valid=0;
      end
    else
      OAM_valid=0;
   end

/* start doing crc10 check after first 3 bytes behide header is in data registers already */
always@(OAM_CELL or count_byte or OAM_CRC)
   begin
     if(count_byte==8)
       begin
         if(OAM_CELL)
    OAM_CRC=1;
  else OAM_CRC=0;
       end
     else OAM_CRC=OAM_CRC;
   end
 

always@(OAM_CELL or count_byte or OAM_CRC3)
   begin
     if(count_byte==9)
       begin
         if(OAM_CELL)
    OAM_CRC3=1;
  else OAM_CRC3=0;
       end
     else OAM_CRC3=OAM_CRC3;
   end

always@( OAM_CELL or count_byte or OAM_CRC2)
     begin
      if(count_byte==3)
       begin
         if(OAM_CELL)
    OAM_CRC2=1;
  else OAM_CRC2=0;
       end

      else OAM_CRC2=OAM_CRC2;
     end

/* shift data from input to output direction, once a clock cycle */
always@(posedge clock )

     begin

      i<=h;
      h<=g;
      g<=out;
      CRC10_2<=crc10;

     end

   assign g2[1]=(OAM_CRC && !OAM_CRC3) ? g[1]^i[3]^i[8] : g[1];
   assign g2[2]=(OAM_CRC && !OAM_CRC3) ? g[2]^i[4]^i[5]^i[6]^i[7]^i[8] : g[2];
   assign g3[1]=OAM_CRC3 ? g2[1]^CRC10_2[3]^CRC10_2[8] : g2[1];
   assign g3[2]=OAM_CRC3 ? g2[2]^CRC10_2[4]^CRC10_2[5]^CRC10_2[6]^CRC10_2[7]^CRC10_2[8] : g2[2];
   assign k=OAM_CRC ? crc10 : h;
   assign OAM_data= OAM_CRC2 ? i : 8'hz; /* not OAM cell, OAM_data is high impedance */
 

endmodule /* CRC_10_CHECK */

/*=================== Declarations ========================*/
module Reminder(clock,DataIn,bit_correction,count_clear,one_cell,check,out,data_out,OAM_Check,OAM_CELL);

/*---------------  Inputs--------------------*/
input  clock;  /* clock */
input  [1:8] DataIn; /* data input */
input  bit_correction; /* indicate bit error needs to be corrected  */
input  count_clear; /* reset counter number to zero */
input one_cell; /* indicate one complete cell */

/*---------------  Outputs-------------------*/
output  check ;    /* indicate if header is error -- 0-right 1-wrong */
output  [1:8] out; /* CRC8 output */
output [1:8] data_out; /* if regulare cell arrives, data output from crc8 out*/
output  OAM_Check; /* OAM_check is high when first three bytes are all 0 */
output OAM_CELL; /* indicate it's OAM cell */

/*---------------- Registers-----------------*/
reg [1:8] a,b,c,d,e; /* 5 input data registers */
reg [1:8] m,n,o,p; /* remainder registers */
reg [1:8] f,out;
reg [1:8] reminder; /* no bit error, remainder is 0 */
reg [39:0] correct_error; /* one bit error fixing talbe */
reg check;
reg OAM_Check,OAM_CELL;

parameter [1:8] con = 8'b01010101; /* constant hex number h'55 */

/*---------------- Nets ---------------------*/
wire [1:8] nx_a,nx_b,nx_c,nx_d,nx_f;
wire OAM_CELL2;
tri [1:8] data_out;

/*==================== Operations ======================*/
always@(posedge clock) /* poly : 100000111 for crc8 */

    begin

 /* shift data from input to output direction, once a clock cycle */
        out <= nx_f;
 f <= nx_a;
 a <= nx_b;
        b <= nx_c;
        c <= nx_d;
        d <= e;
        e <=DataIn;

 /* remainder pattern after 40 bits long division */
        p[1] <= e[1] ^ e[2] ^ e[3];
        o[1] <= d[1] ^ d[3] ^ d[5];
        n[1] <= c[2] ^ c[4] ^ c[6] ^ c[7];
        m[1] <= b[2] ^ b[3] ^ b[5];

 p[2] <= e[2] ^ e[3] ^ e[4];
        o[2] <= d[2] ^ d[4] ^ d[6];
        n[2] <= c[3] ^ c[5] ^ c[7] ^ c[8];
        m[2] <= b[3] ^ b[4] ^ b[6];

 p[3] <= e[3] ^ e[4] ^ e[5];
        o[3] <= d[1] ^ d[3] ^ d[5] ^ d[7];
        n[3] <= c[4] ^ c[6] ^ c[8] ;
        m[3] <= b[1] ^ b[4] ^ b[5] ^ b[7];

 p[4] <= e[4] ^ e[5] ^ e[6];
        o[4] <= d[1] ^ d[2] ^ d[4] ^ d[6] ^ d[8];
        n[4] <= c[5] ^ c[7]  ;
        m[4] <= b[1] ^ b[2] ^ b[5] ^ b[6] ^ b[8];

 p[5] <= e[1] ^ e[5] ^ e[6] ^ e[7];
        o[5] <= d[2] ^ d[3] ^ d[5] ^d[7];
        n[5] <= c[1] ^ c[6] ^ c[8];
        m[5] <= b[2] ^ b[3] ^ b[6] ^ b[7];

 p[6] <= e[2] ^ e[6] ^ e[7] ^ e[8];
        o[6] <= d[1] ^ d[3] ^ d[4] ^ d[6] ^ d[8];
        n[6] <= c[2] ^ c[7];
        m[6] <= b[3] ^ b[4] ^ b[7] ^ b[8];

 p[7] <= e[2] ^ e[7] ^ e[8];
        o[7] <= d[1] ^ d[2] ^ d[3] ^ d[4] ^ d[7];
        n[7] <= c[1] ^ c[2] ^ c[3] ^ c[4] ^ c[6] ^ c[7] ^ c[8];
        m[7] <= b[2] ^ b[3] ^ b[4] ^ b[8];

 p[8] <= e[1] ^ e[2] ^ e[8];
        o[8] <= d[2] ^ d[4] ^ d[8];
        n[8] <= c[1] ^ c[3] ^ c[5] ^ c[6] ^ c[8];
        m[8] <= b[1] ^ b[2] ^ b[4];

        reminder<= m ^ n ^ o ^ p ^ e ^ con;
 check <=|(m ^ n ^ o ^ p ^ e ^ con) ; /* check final remainder */

end

/* check if first 3 bytes to see if it is OAM cell */
always@(one_cell or nx_a or nx_b or nx_f or check)
   begin
     OAM_Check<=0;
    if(one_cell)
       begin
       if(nx_a==8'h00 && nx_f==8'h00 && nx_b==8'h00 && !check)
       OAM_Check<=1;
       else OAM_Check<=0;
       end
   end

/* one bit error correction talbe */
always@(bit_correction or reminder)
  begin correct_error=40'b0;
  if (bit_correction)
    begin

     case(reminder)
        8'h01 : correct_error[0]=1;
        8'h02 : correct_error[1]=1;
        8'h04 : correct_error[2]=1;
        8'h08 : correct_error[3]=1;
        8'h10 : correct_error[4]=1;
        8'h20 : correct_error[5]=1;
        8'h40 : correct_error[6]=1;
        8'h80 : correct_error[7]=1;
        8'h07 : correct_error[8]=1;
        8'h0e : correct_error[9]=1;
        8'h1c : correct_error[10]=1;
        8'h38 : correct_error[11]=1;
        8'h70 : correct_error[12]=1;
        8'he0 : correct_error[13]=1;
        8'hc7 : correct_error[14]=1;
        8'h89 : correct_error[15]=1;
        8'h15 : correct_error[16]=1;
        8'h2a : correct_error[17]=1;
        8'h54 : correct_error[18]=1;
        8'ha8 : correct_error[19]=1;
        8'h57 : correct_error[20]=1;
        8'hae : correct_error[21]=1;
        8'h58 : correct_error[22]=1;
        8'hb6 : correct_error[23]=1;
        8'h6b : correct_error[24]=1;
        8'hd6 : correct_error[25]=1;
        8'hab : correct_error[26]=1;
        8'h51 : correct_error[27]=1;
        8'ha2 : correct_error[28]=1;
        8'h43 : correct_error[29]=1;
        8'h86 : correct_error[30]=1;
        8'h0b : correct_error[31]=1;
        8'h16 : correct_error[32]=1;
        8'h2c : correct_error[33]=1;
        8'h58 : correct_error[34]=1;
        8'hb0 : correct_error[35]=1;
        8'h67 : correct_error[36]=1;
        8'hce : correct_error[37]=1;
        8'h9b : correct_error[38]=1;
        8'h31 : correct_error[39]=1;
        default : correct_error=40'b0;
     endcase
 end
end

/* indicate FSM module if it is OAM cell */
always@(posedge clock)
OAM_CELL<=OAM_CELL2;

assign nx_f=bit_correction ? f[1:8]^correct_error[39:32] : f[1:8];
assign nx_a=bit_correction ? a[1:8]^correct_error[31:24] : a[1:8];
assign nx_b=bit_correction ? b[1:8]^correct_error[23:16] : b[1:8];
assign nx_c=bit_correction ? c[1:8]^correct_error[15:8] : c[1:8];
assign nx_d=bit_correction ? d[1:8]^correct_error[7:0] : d[1:8];
assign OAM_CELL2=(count_clear || bit_correction || one_cell) ? OAM_Check : (OAM_CELL|0);
assign data_out=OAM_CELL ? 8'bz : out; /* if it is OAM cell, output is high impedance */

endmodule /* Reminder */

Read -f Verilog CRCoAM.v

current_design = CRC_OAM

target_library = {"ms080cmosxCells_XXW.db"}
link_library = {"ms080cmosxCells_XXW.db"}

set_dont_use ms080cmosxCells_XXW/PULLUP
set_dont_use ms080cmosxCells_XXW/PULLDWN
/*set_dont_use ms080cmosxCells_XXW/EDFFR*/

set_operating_conditions -library "ms080cmosxCells_XXW" "T125_V4.5"

set_driving_cell -cell "DFF" -pin "Q" all_inputs() - clock

port_load = 0.5 + 3 * load_of (ms080cmosxCells_XXW/DFF/D)
set_load port_load all_outputs()

Create_clock -period 21.8 -waveform {0 10.9} clock
set_clock_skew  -uncertainty 0.3 clock

set_input_delay 2.0 -clock clock all_inputs() - clock

set_output_delay 1.65 -clock clock all_outputs()

set_max_area 0

replace_synthetic -ungroup

/*compile -map_effort low*/

check_design
check_timing

/*characterize -constraints {u2}*/
current_design = ATM_Cell_Controller
/*replace_synthetic -ungroup*/
 
 
 

/*-----------------------------------------------------------*/
/*     2. Re-Compile to Optimize the FSM Design:             */
/*         -specify state vector,                            */
/*         -specify state encoding,                          */
/*         -specify encoding style for unencoded states,     */
/*         -seperate FSM from other logic(if necessary),     */
/*         -extract state table,                             */
/*         -minimize FSM states.                             */
/*-----------------------------------------------------------*/
/*group -fsm -design_name ATM_Cell_Controller*/

set_fsm_state_vector {cd_state_reg[0] cd_state_reg[1] /*second_time_reg*/}
set_fsm_encoding {"hunt=2#00" "presync=2#01" "sync=2#10" "invalid_output=2#11"}
set_fsm_encoding_style auto

/* Create a seperate FSM hierarchy level, if applicable */
/*current_design = ATM_Cell_Controller*/

/* Create an FSM state-table from  */
/* HDL, minimize transition logic, */
/* and display FSM attributes.     */

group -fsm -design_name fsm_group

current_design = fsm_group

extract -minimize
report_fsm

/* Now resynthesize the design to meet constraints,     */
/* and try to best achieve the goal:                    */
/* -perform state minimization                          */
/* -map_effort specifies how much optimization effort   */
/* there is, i.e. low, medium, or high.                 */
/*      Use high to squeeze out those last picoseconds. */
/* -verify_effort specifies how much effort to spend    */
/* making sure that the input and output designs        */
/* are equivalent logically                             */

set_fsm_minimize true
compile -map_effort high -verify -verify_effort high

/* Compile at the top level if a seperate */
/* FSM hierarchy level was created above. */
current_design = ATM_Cell_Controller

/*replace_synthetic -ungroup*/

/* compile -map_effort medium -verify -verify_effort medium */
compile -map_effort high -verify -verify_effort high

current_design = CRC_OAM

/*characterize -constraints {u2}
current_design = ATM_Cell_Controller
compile -map_effort high -verify_effort high

current_design = CRC_OAM

characterize -constraints {u3}
current_design = COUNT_CELL
compile -map_effort high -verify -verify_effort high

current_design = CRC_OAM

characterize -constraints {u4}
current_design = COUNT_BYTE
compile -map_effort high -verify -verify_effort high

current_design = CRC_OAM

characterize -constraints {u5}
current_design =  Reminder
compile -map_effort high -verify -verify_effort high

current_design = CRC_OAM

characterize -constraints {u6}
current_design = CRC_10_CHECK
compile -map_effort high -verify -verify_effort high

current_design = CRC_OAM

compile -map_effort high -verify -verify_effort high

/*-----------------------------------------------------------*/
/*     3. Verify Design Timing:                              */
/*         -check slowest paths with worst case library.     */
/*-----------------------------------------------------------*/
/*check_design
check_timing*/
report_timing -max_paths 3

/*-----------------------------------------------------------*/
/*     4. Re-Compile with Best Case Library:                 */
/*         -specify current technology library,              */
/*         -specify new technology library,                  */
/*         -re-map current design to new library,            */
/*         -specify new design constraints,                  */
/*         -compile to correct design rule violations.       */
/*-----------------------------------------------------------*/

target_library = {"ms080cmosxCells_XXB.db"}
link_library = {"ms080cmosxCells_XXW.db"}
translate -verify -verify_effort medium

set_dont_use ms080cmosxCells_XXB/PULLUP
set_dont_use ms080cmosxCells_XXB/PULLDWN
set_dont_use ms080cmosxCells_XXB/EDFFR

set_operating_conditions -library "ms080cmosxCells_XXB" "T-55_V5.5"

set_fix_hold clock
compile -only_design_rule -incremental

/*-----------------------------------------------------------*/
/*     5. Verify Final Design Hold Timing:                   */
/*         -check fastest paths with best case library,      */
/*         -write out sdf file for best case design.         */
/*-----------------------------------------------------------*/

report_timing -delay min

write_timing -output CRC_min.sdf -format sdf-v2.1

/*-----------------------------------------------------------*/
/*     6. Verify Final Design Setup Timing:                  */
/*         -specify current technology library,              */
/*         -specify new technology library,                  */
/*         -re-map current design to new library,            */
/*         -specify new design constraints,                  */
/*         -check slowest paths with worst case library,     */
/*         -write out sdf file for worst case design.        */
/*-----------------------------------------------------------*/

target_library = {"ms080cmosxCells_XXW.db"}
link_library = {"ms080cmosxCells_XXB.db"}
translate
set_operating_conditions -library "ms080cmosxCells_XXW" "T125_V4.5"
report_timing

write_timing -output CRC_max.sdf -format sdf-v2.1

write -format verilog -hierarchy -output CRCFinal.v

/* create_schematic -size infinite -gen_database
 create_schematic -size infinite -symbol_view
 create_schematic -size infinite -hier_view
 create_schematic -size infinite -schematic_view
 plot_command = "cat>dc_plot.ps"
 plot -hierarchy
exit*/