** Lecture Plan for the semester Jan-May, 2009 of B.Tech.(IT) students

Lecture Plan for the semester Aug-Dec, 2008 of B.Tech.(CSE) students

E1. List of Experiments

1. Introduction to VHDL

2. Structural Modeling

3. Generate Statement

4. Data Type

5. Design of Four Bit Adder

6. Basic Concept of Operators & Attributes

7. Design of Carry Look Ahead Adder circuit using VHDL

8. Design of BCD Adder using VHDL

9. Design of 7-segment display decoder circuit using VHDL

10. Concurrent Design & Design of Decoders

11. Timing model

12. Control Structure

12-A. Design of Register and Counters

13. Structure of Memory and I/O subsystem

14. Introduction of Micro Programmed Controller

15. Overview of PAL, PLA, FPGA & CPLD

16. Register Transfer Level Systems

17. Design of Serial Adder with Accumulator and design of binary Multiplier

18. Signal vs Variables

19. Tutorial on Subprograms, Packages and Functions

20. Model of Delay

E.1 List of Assignment -1

E.2 List of Assignment -2

E.3 List of Assignment -3

A.1 Xilinx Foundatin Series

A.2 Altera University Programme