Recent Graduate/Student

Educational Qualifications:

Indian Institute of Technology Bombay, India M Tech, Electrical Engineering Specialization: Microelectronics Marks : 8.89 (On 10 point scale) Courses : VLSI Design, System Hardware Design, Modern Elecronic Design Techniques, Computer-Aided Analysis and Design, Hardware Description Language, Digital Signal Processing, Physical Electronics, Physics of Transistor, VLSI Technology and Microelectronics Lab.

July 2000 - Jan 2002

Indian Institute of Technology Delhi, India Masters of Science, Physics Marks : 8.86 (On 10 point scale) Courses : Solid State Physics, Semiconductor Physics, Analog Electronics, Advance Electronics (Digital), Microelectronics, Optoelectronics, Physics of Thin Films.

July 1998 - May 2000

Motilal Nehru College, University of Delhi, India Bachelor of Science, Physics(H) Marks : 74.5 %

July 1995 - May 1998

• Jitter Analysis, Design and Modeling of PLL (M Tech)
• Bulk & Surface Passivation and Antireflection Coating of Silicon (M Sc)
• Best-fit-curve Generation for a given Data-table and goodness of fit (B Sc)

• Implementation of Interrupt Controller Unit of 80186 using Verilog.
• Implementation of ALU (16 bit) using Verilog.
• Implementation of Single slope ADC, Triangular wave and Square wave generator using SPICE.
• Design of two stage CMOS OP-AMP for a given specifications, using SPICE.
• Implementation of MOV instruction of 8085 and IEEE GPIB source and acceptor handshake using IRSIM.
• Layout of circuit of MOV instruction of 8085 (implemented in IRSIM) using Magic.
• Design of complete CMOS process for 70 nm technology using SUPREM-IV.
• Design of NMOS for 250 nm technology in TSUPREM-IV and study of Id-Vd, Id-Vg, VT roll-off, and subthreshold swing with respect to different channel implant depth were done using MIDICI.
• Implementation of BFS, DFS and MST using C++.
• Design of Bandgap Reference.*

• R. S. Narayanan Scholarship (1998-1999)
• Prof. Vidya Bhusan Scholarship (1999-2000)
• Prof. Neeraj Srivastave Award (2000)
• GATE 2000 : Scored 98.92 percentile in the Graduate Aptitude Test in Enginnering (Physics) with an all India rank of 14.
• Qualified in national level junior reserch fellowship/lecturership eligibility test in Physics conducted by CSIR, India in the year 2000.
• Fellow of Tata Consultancy Services, at I I T Bombay, July 2000 - January 2002

• VLSI Design Tools/simulators:
  
  Xilinx(VHDL/Verilog)*, SPICE, SABER, IRSIM, MAGIC
• Device and Process Simulators:
  MIDICI, PISCES, TSUPREM-IV, SUPREM-IV
• Software Experience:
  
  • Worked on Solaris, Linux/Unix, Windows platform
  • Familier with C, C++, HTML

• Date of Birth : March 1st, 1978
• Sex : Male
• Marital Status: Single
• Citizenship : Indian
• Hobbies : Reading books, Listening Indian Music
• Interest : Deep interest in learning issues involved with RF Design

Available on request.