• 3.5 years of Research and Development experience in VLSI/ASIC/SoC Design and Testing in domain of Optical Networks and Computer Architecture.

• Have been working on the research and development project of multi-million gates which is Ethernet-Over-Sonet (OC-48) chip at TranSwitch Corporation, and have owned full responsibility of a 200k gates module in the project.

• Have worked on designing large complex timing critical blocks, algorithm implementation, developing complete verification environment for multi-million gate designs.

Am young and have an aggressive approach towards challenges with the single objective of achieving progressive results and excellence in a Team or Individually.

• Chip Specification
• Architecture and Partitioning
• Digital Design and RTL Coding in Verilog/VHDL
• Design and Implementation of Bus Functional Models
• Verilog, VHDL, C, Perl Scripting and Shell Scripting
• Functional Simulation and Verification of Design
• Experience in SDH/SONET, PCI(X) standards
• Technical Societies Membership: IEEE (USA) and IETE (New Delhi, India).

TranSwitch Corporation (India Design Center-New Delhi, India)

Member Technical Staff (VLSI R&D)

Duration:

Oct, 2000 - Till Date

Project Summary:

At TranSwitch, I have worked on two major ASICs which are:

1. A research and development project on OC-48 Level Ethernet-Over-Sonet Mapper (Industry Name as EtherMap-48). In this chip, I am involved with an IP core POP which processes the Path Overheads at granularity of OC-1 and do path protection switching or bridging. This device is based on IP Core methodology and Scalable from OC-1 to OC-192 on 0.13u fabrication technology. (Current Project)
2. Another ASIC is an OC-3 level E1/T1 over Sonet Mapper (Industry Name as TEMX21/28). In this chip, I was involved with the major module known as DEMAPPER which de-mux the STM-1/STS-3 data to E1/T1 channels and also terminates and process Lower Order Path Overhead Bytes.

Responsibilities:

My responsibilities as a front-end VLSI R&D Engineer includes specifications, chip architecture and block partitioning, design and RTL Coding of individual blocks, Integration and Integration Testing, Generation of Block and Top Level Verification Environments (automated by writing various perl, shell and C scripts), verification, simulation, design debugging, synthesis and STA. Design of complex datapath blocks and algorithmic design and implementation.

Altera Corporation (SanJose, USA)

Consultant (VLSI Design)

Duration:

Apr, 2000 - Jun, 2000

Project Summary:

1. This project was done at client's site (Altera Corporation, Sanjose, CA). Altera's PCI(X) core (targeted for FPGA) was without Decoder and Configuration Space modules so the main task was to design and code these modules as per the requirements of Altera. Other than above design, I was involved with development of full verification environment and TestPlan for Altera's PCI(X) chip including development of User Logic Interface (Compaq's CREX) Bus Functional Models.

Responsibilities:

Was involved in Design and RTL coding in verilog of Decoder and Configuration Space, CREX Bus Functional Models, Verification Environment and verification in Altera's PCI(X) chip.

DCM Technologies (Gurgaon, India)

Sr. Design Engineer (VLSI Design)

Duration:

Jul, 1999 - Mar, 2000

Jul, 2000 - Sep, 2000

Project Summary:

1. X-BUS Bus Functional Models: X-Bus is an in-house product of DCM Technologies. It is an internal ASIC expansion bus to be used in PCI/PCI(X) cores. This bus interfaces with the internal master-target and buffer manager modules. The X-BUS Master will initiate 32/64 bit memory, I/O and configuration transactions on X-BUS Target modules.
2. PCI(X)-to-PCI Translator: It is a scale down version of bridge that has PCI(X) on primary and PCI on secondary side. Primary and secondary interfaces of this design work at same frequency. It was an IP of DCM Technologies targeted towards the clients with existing PCI devices, which could be made compatible to PCI(X) 1.0 specifications without any change in the PCI chip but the PCI card.
3. PCI(X) core: It enables a back-end application such as Ultra3 SCSI, Fiber Channel and Gigabit Ethernet to avail the high bandwidth provided by PCI(X) as compared to PCI. This logic isolates the back-end application or User Logic from the complexities of the PCI(X) protocols. The Core is basically of 32 / 64-bit and has master target capability.
4. User Logic Interface Bus Functional Models: ULI Master has an interface as defined in Altera's pci_c function and specifications. This model was used to facilitate the functional verification and simulation of the PCI(X) core. Master can initiate both 32-bit as well as 64-bit Config, IO and memory transactions.

Responsibilities:

Design and RTL coding in Verilog, of above said modules including design of complex datapath blocks and algorithmic design and implementation. Was responsible for development of an automated verification environment using perl for random testcase generator. Functional Testing and Verification of PCI(X) Core in PCI mode using Bus Functional Models.

Has always been an active participant in the extra curricular activities, articulated below are some of the few significant achievements:

• Delivered Guest Lectures on VLSI Design and Market Trends at some organizations and own university.

• Active participation in Table Tennis and cricket at school and college level.

• Acted as Coordinator - Placement Committee and Editor - College Technical Magazine at University Level.

• Several Technical Papers published in University's technical magazine.

• Involved in training of Team-track (Defect Prevention Tool) to all the employees of DCM Technologies.

• Functional Area Representative for SEI-CMM level - 5 assessments of DCM Technologies.

• Selected for US on-site assignment for Altera Corporation.

• Technical Societies Membership: IEEE (USA) and IETE (New Delhi, India).