A Tutorial using vmake and make

This is a tutorial of how to use make with VHDL source files and Model Technology's ModelSim simulator. This tutorial is suppose to make your life easier. Let's begin.

Problem:

You have a VHDL project with many source files. Many of the design units are dependent on one another. For instance, Here is our design structure.

tb_one is our testbench entity and it has an architecture named test. The test architecture instantiates 3 components; cpu, pnet_read, and pnet_write. The entity cpu has one architecture named beh. The entity pnet_read has 2 architectures beh and rtl. The entity pnet_write has 2 architectures, beh and dummy. The rtl architecture of the pnet_read entity instantiates 2 components named read_frame and write_data. The entity read_frame has 2 architectures, gates and rtl. The entity write_data has 2 architectures, gates and rtl. The beh architecture of the cpu entity uses the package p. The gates and rtl architectures of the read_frame entity uses the package p. The gates and rtl architectures of the write_data entity uses the package p.

The only caveat is you must compile the structure once by hand...or do you? For simple designs that are compiled into the work library and all source files exist in one directory then Makefile.virgin should build your Makefile.work. Makefile.work is the desciption of your system as ModelSim understands it at this point in time. If you compile more design units then you will have to create a new Makefile.work.

A simple makefile consists of "rules" with the following syntax:

 
target ... : dependencies ...
        command
        ...
        ...

 
# Define path to each library
LIB_IEEE = /asic/tools/modelsimEE/modeltech_5.2e/sunos5/../ieee
LIB_WORK = work

LIB = work

VCOM = vcom -93
VLOG = vlog

ALL: *.vhd
	$(VCOM) -just p *.vhd
	$(VCOM) -just b *.vhd
	$(VCOM) -just e *.vhd
	$(VCOM) -just a *.vhd
	$(VCOM) -just c *.vhd
	vmake $(LIB) > Makefile.$(LIB)

This will compile all .vhd files and build a Makefile.work for you. It could fail for the following reasons:

1. Syntax errors in your VHDL files

2. Makefile.work exists

Now, link the file Makefile to Makefile.work

%ln -s Makefile.work Makefile

make searches for "Makefile" when it is run, this saves us typing. Now make your project:

%make

Wasn't that easy? Let's play around.

%touch tb_one_test.vhd

%make

This should only make the test architecture. Did it?

%touch tb_one.vhd

%make

This should only make the tb_one entity and its' test architecture. Did it?

Are you getting the picture? Only those files that are dependent are made.

I hope this has helped!

emmett_bearden@yahoo.com end tutorial vmake;