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Software Projects
8-Bit Parallel-Load Shift Register
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A Johnson counter contains the basic structure of a shift register which is made up by a chain of D-FFs. Beginning with the LSB of a register (a number of D-FFs) each D-FF output can be connected to the data input of the D-FF with next higher weight.
Applications of shift registers will be found in serial communication interfaces. The receiver input device will clock in a data stream of sequenced bits and a parallel word will be accessed by internal processes. A sender will clock out a parallel stored word over a serial register output. Simple multiply and division operations can be performed by a shift register. A multiplication by two will be done with a shift left by one bit.
A VHDL-module which models a shift register type SN74HC166 has to be implemented with a CPLD XC95108.
Pseudo-random genterator:
Another shift register or ring counter application that is simple in terms of next state lobic is the linear feedback shift register (LFSR). The next state lobic is formed by XOR gates. The sequence of states appears to be random. In order to avoid a stop of sequence an appropriate set condition has to be applied and a self correcting circuit has to be connected to the load input.
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Implemented at Hochschule fuer angewandet Wissenschaft Hamburg
Nov 19, 2000 - Nov 26, 2001
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