<![CDATA[-- Author: M. Gomez
-- Date : 10/29/1999
-- Rev No: 1.1
-- File : arm7.vhdl
-- Following is the arm7 entity declaration and
-- architectural definition
--
USE work.arm7_pkg.ALL;
USE work.arm7_time_pkg.ALL;
ENTITY arm7 IS
GENERIC (
Tp : time := Tps -- Establish standard unit propogation delay
-- time for use throughout the design.
);
PORT(
mclk : IN io;
nWait : IN io;
nrw : OUT io;
nbw : OUT io;
nIrq : IN io;
nFiq : IN io;
nReset : IN io;
abort : IN io;
nTrans : OUT io;
nMReq : OUT io;
seq : OUT io;
lock : OUT io;
nm : OUT io_vec(4 DOWNTO 0);
data : IN data_t;
dout : OUT data_t;
dbe : IN io;
nEnOut : OUT io;
adrs : OUT adrs_t;
ale : IN io);
END ENTITY arm7;
ARCHITECTURE behav OF arm7 IS
SIGNAL a_bus : data_t;
SIGNAL alu_bus : data_t;
SIGNAL b_bus : data_t;
SIGNAL d_bus : data_t;
SIGNAL pc_bus : adrs_t;
SIGNAL inc_bus : adrs_t;
SIGNAL inst_bus : inst_bus_t;
SIGNAL alu_ctrl : alu_ctrl_t;
SIGNAL regBank_ctrl : regBank_ctrl_t;
SIGNAL adrsReg_ctrl : adrsReg_ctrl_t;
SIGNAL adrsReg_ctrl_rtn : adrsReg_ctrl_rtn_t;
SIGNAL adrsInc_ctrl : adrsInc_ctrl_t;
SIGNAL wdReg_ctrl : wdReg_ctrl_t;
SIGNAL wdReg_ctrl_rtn : wdReg_ctrl_rtn_t;
SIGNAL rdReg_ctrl : rdReg_ctrl_t;
SIGNAL rdReg_ctrl_rtn : rdReg_ctrl_rtn_t;
SIGNAL cc : cc_t;
SIGNAL cin : io;
SIGNAL cout : io;
SIGNAL sysclk : io;
COMPONENT alu IS
GENERIC ( Tp : time );
PORT (
alu_bus : OUT data_t;
cc : OUT cc_t;
a_bus : IN data_t;
b_bus : IN data_t;
d_bus : IN data_t;
cin : IN io;
alu_ctrl : IN alu_ctrl_t);
END COMPONENT alu;
COMPONENT regBank IS
GENERIC (Tp : time );
PORT (
a_bus : OUT data_t;
b_bus : OUT data_t;
cout : OUT io;
pc_bus : OUT data_t;
alu_bus : IN data_t;
inc_bus : IN data_t;
regBank_ctrl : IN regBank_ctrl_t;
nReset : IN io;
sysClk : IN io);
END COMPONENT regBank;
COMPONENT adrsReg IS
GENERIC (Tp : time);
PORT (
adrs : OUT adrs_t;
adrsReg_ctrl_rtn : IN adrsReg_ctrl_rtn_t;
inc_bus : IN adrs_t;
pc_bus : IN adrs_t;
adrsReg_ctrl : IN adrsReg_ctrl_t;
nReset : IN io;
sysClk : IN io);
END COMPONENT adrsReg;
COMPONENT wdReg IS
GENERIC (Tp : time);
PORT (
dout : OUT data_t;
nEnOut : OUT io;
wdReg_ctrl_rtn : OUT wdReg_ctrl_rtn_t;
b_bus : IN adrs_t;
dbe : IN io;
wdReg_ctrl : IN wdReg_ctrl_t;
nReset : IN io;
sysClk : IN io);
END COMPONENT wdReg;
COMPONENT rdReg IS
GENERIC (Tp : time);
PORT (
b_bus : OUT data_t;
inst_bus : OUT inst_bus_t;
rdReg_ctrl_rtn : OUT rdReg_ctrl_rtn_t;
data : IN data_t;
rdReg_ctrl : IN rdReg_ctrl_t;
nReset : IN io;
sysClk : IN io);
END COMPONENT rdReg;
COMPONENT decAndCtrl IS
GENERIC (Tp : time);
PORT (
nRW : OUT io;
nBW : OUT io;
nTrans : OUT io;
nMReq : OUT io;
seq : OUT io;
lock : OUT io;
nM : OUT io_vec( 4 DOWNTO 0);
adrsReg_ctrl : OUT adrsReg_ctrl_t;
alu_ctrl : OUT alu_ctrl_t;
wdReg_ctrl : OUT wdReg_ctrl_t;
rdReg_ctrl : OUT rdReg_ctrl_t;
adrsReg_ctrl_rtn : IN adrsReg_ctrl_rtn_t;
wdReg_ctrl_rtn : IN wdReg_ctrl_rtn_t;
rdReg_ctrl_rtn : IN rdReg_ctrl_rtn_t;
nIRQ : IN io;
nFIQ : IN io;
nRESET : IN io;
abort : IN io;
sysClk : IN io);
END COMPONENT decAndCtrl;
COMPONENT clkBuf IS
GENERIC (Tp : time);
PORT (
sysClk : OUT io;
mClk : IN io;
nWait : IN io);
END COMPONENT clkBuf;
BEGIN
U0 : clkBuf
GENERIC MAP (Tp)
PORT MAP ( sysClk, mClk, nWait);
U1 : alu
GENERIC MAP (Tp)
PORT MAP ( alu_bus, cc, a_bus, b_bus, d_bus, cin, alu_ctrl);
U2 : regBank
GENERIC MAP (Tp)
PORT MAP (a_bus, b_bus, cout, pc_bus, alu_bus, inc_bus, regBank_ctrl, nReset, sysClk);
U3 : adrsReg
GENERIC MAP (Tp)
PORT MAP (adrs, adrsReg_ctrl_rtn, inc_bus, pc_bus, adrsReg_ctrl, nReset, sysClk);
U4 : wdReg
GENERIC MAP (Tp)
PORT MAP (dout, nEnOut, wdReg_ctrl_rtn, b_bus, dbe, wdReg_ctrl, nReset, sysClk);
U5 : rdReg
GENERIC MAP (Tp)
PORT MAP (b_bus, inst_bus, rdReg_ctrl_rtn, data, rdReg_ctrl, nReset, sysClk);
U6 : decAndCtrl
GENERIC MAP (Tp)
PORT MAP ( nRW, nBW, nTrans, nMReq, seq, lock, nM,
adrsReg_ctrl, alu_ctrl, wdReg_ctrl, rdReg_ctrl,
adrsReg_ctrl_rtn, wdReg_ctrl_rtn, rdReg_ctrl_rtn,
nIRQ, nFIQ, nRESET, abort, sysClk);
END ARCHITECTURE behav;
]]>