<![CDATA[-- Author: M. Gomez
-- Date : 10/29/1999
-- Rev No: 1.1
-- File : arm7_pkg.vhdl
-- Following is the CSE517 package declaration and definition
-- During block development, this package is to be used by
-- all design blocks to insure common and consistent
-- type declarations among all blocks.
--
-- To use this package include the following line into each
-- block that makes use of this set of package declarations:
-- USE work.arm_pkg.ALL;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
PACKAGE arm7_pkg IS
-- Establish a standard IO type for use by all signals
SUBTYPE io IS std_logic;
SUBTYPE io_vec IS std_logic_vector;
CONSTANT Tps : time := 10 ns;
-- Establish some usefull data width constants
CONSTANT adrs_bus_width : integer := 32;
CONSTANT adrs_max : integer := 2**adrs_bus_width-1;
CONSTANT adrs_min : integer := 0;
CONSTANT memory_size : integer := 2**adrs_bus_width;
CONSTANT data_width : integer := 8;
CONSTANT data_max : integer := 2**data_width-1;
CONSTANT data_min : integer := 0;
CONSTANT word_width : integer := 4* data_width;
CONSTANT word_max : integer := 2**word_width-1;
CONSTANT word_min : integer := 0;
CONSTANT data_bus_width : integer := word_width;
CONSTANT reg_width : integer := word_width;
CONSTANT reg_max : integer := word_max;
CONSTANT reg_min : integer := 0;
CONSTANT pipelineLength : integer := 5;
SUBTYPE adrsRange IS natural RANGE adrs_bus_width-1 DOWNTO 0;
SUBTYPE adrsRangeLessLeft IS adrsRange RANGE adrsRange'pred(adrsRange'left) DOWNTO adrsRange'right;
SUBTYPE adrsRangeLessRight IS adrsRange RANGE adrsRange'left DOWNTO adrsRange'succ(adrsRange'right);
SUBTYPE dataRange IS natural RANGE data_bus_width-1 DOWNTO 0;
SUBTYPE dataRangeLessLeft IS dataRange RANGE dataRange'pred(dataRange'left) DOWNTO dataRange'right;
SUBTYPE dataRangeLessRight IS datarange RANGE datarange'left DOWNTO dataRange'succ(dataRange'right);
SUBTYPE regRange IS natural RANGE data_bus_width-1 DOWNTO 0;
SUBTYPE regRangeLessLeft IS regRange RANGE regRange'pred(regRange'left) DOWNTO regRange'right;
SUBTYPE regRangeLessRight IS regRange RANGE regRange'left DOWNTO regRange'succ(regRange'right);
-- The following subtype declarations are to be used to define of the
-- bus a information in the design.
SUBTYPE adrs_t IS io_vec(adrsRange);
SUBTYPE data_t IS io_vec(dataRange);
SUBTYPE reg_t IS io_vec(regRange);
TYPE cc_t IS RECORD
n : io;
z : io;
c : io;
v : io;
irq : io;
fiq : io;
mode : io_vec (4 DOWNTO 0);
END RECORD cc_t;
-- Establish each address bus as a subtype of the common
-- type adrs_t so that operations can be easily coded across
-- multiple data busses.
SUBTYPE a_t IS adrs_t;
SUBTYPE pc_bus_t IS adrs_t;
SUBTYPE inc_bus_t IS adrs_t;
-- Define what an instruction looks like
TYPE opcode_t IS (no_op, add, adc, sub, sbc, rsb, rsc, cmp, cmn, tst, teq, -- Modified 10/28/99 MG
andr, eor, orr, bic, lsl, lsr, asr, mov, -- Modified 10/28/99 MG
ldr, ldrb, str, strb, beq, bne, swp, swi); -- Modified 10/28/99 MG
-- Establish each data bus as a subtype of the common
-- type data_t so that operations can be easily coded across
-- multiple data busses.
SUBTYPE alu_bus_t IS data_t; -- Modified 10/29/99 MG
SUBTYPE a_bus_t IS data_t;
SUBTYPE b_bus_t IS data_t;
SUBTYPE d_bus_t IS data_t;
SUBTYPE inst_bus_t IS opcode_t;
TYPE adrsMode_t IS (immed, reg); -- Modified 10/29/99 MG
TYPE regName_t IS (r0, r1, r2, r3, r4, r5, r6, r7, r8, -- Modified 10/28/99 MG
r9, r10, r11, r12, r13, r14, r15, cpsr); -- Modified 10/28/99 MG
SUBTYPE arg_t IS integer;
TYPE inst_t IS RECORD
baseInst : opcode_t ;
adrsMode : adrsMode_t;
r1 : regName_t;
r2 : regName_t;
arg1 : arg_t;
arg2 : arg_t;
END RECORD inst_t;
-- Declare ALU control commands for each of the
TYPE alu_ops_t IS (add, adc, sub, sbc, rsb, rsc, and_op, or_op, eor, -- Modified 10/28/99 MG
passA, passB, passInst); -- Modified 10/28/99 MG
TYPE b_bus_ctrl_t IS ( b_bus, inst_bus); -- Modified 10/28/99 MG
-- Declare a single record to be passed between controller and
-- register bank for all actions
TYPE alu_ctrl_t IS RECORD -- Modified 10/28/99 MG
alu_ops : alu_ops_t; -- Modified 10/28/99 MG
b_bus_ctl : b_bus_ctrl_t; -- Modified 10/28/99 MG
END RECORD alu_ctrl_t; -- Modified 10/28/99 MG
-- Declare a single record to be passed between controller and
-- register bank for all actions
TYPE regBank_src_t IS (alu_bus, inc_bus);
TYPE regBank_ops_t IS (lsl, lsr, asr);
TYPE regBank_ctrl_t IS RECORD
a_bus_out : regName_t;
b_bus_out : regName_t;
loadReg : regName_t;
regBank_src : regBank_src_t;
regBank_ops : regBank_ops_t;
loadN : boolean;
loadZ : boolean;
loadC : boolean;
loadV : boolean;
loadI : boolean;
loadF : boolean;
loadMode : boolean;
END RECORD regBank_ctrl_t;
TYPE adrsReg_ctrl_t IS RECORD
loadReg : boolean;
END RECORD adrsReg_ctrl_t;
TYPE adrsReg_ctrl_rtn_t IS RECORD
adrs_valid : boolean;
END RECORD adrsReg_ctrl_rtn_t;
TYPE adrsInc_ctrl_t IS RECORD
loadReg : boolean;
END RECORD adrsInc_ctrl_t;
-- Declare a single record to be passed between controller and
-- register bank for all actions
TYPE wdReg_ctrl_t IS RECORD
loadReg : boolean;
END RECORD wdReg_ctrl_t;
TYPE wdReg_ctrl_rtn_t IS RECORD
data_written : boolean;
END RECORD wdReg_ctrl_rtn_t;
-- Declare a single record to be passed between controller and
-- register bank for all actions
TYPE dataSize_t IS (word, byte);
TYPE rdReg_ctrl_t IS RECORD
loadReg : boolean;
dataSize : dataSize_t;
END RECORD rdReg_ctrl_t;
TYPE rdReg_ctrl_rtn_t IS RECORD
data_ready : boolean;
END RECORD rdReg_ctrl_rtn_t;
TYPE instpipeline IS ARRAY(1 TO pipelineLength) OF inst_t;
TYPE cc_reg_t IS (no_op);
END PACKAGE arm7_pkg;]]>