Introduction to Electronic Packaging

Yu Gu. Dept of Mechanical Engineering, SUNY at Stony Brook

This web page is a rough summary to the background knowledge of electronic packaging. It is a course presentation by the author at April 2000 in Stony Brook University. Content include brief introductions on IC history, packaging technologies, flip-chip assembly, electroless redistribution, material properties, and challenges we faced. Many of the pictures are referred from other people's work. Please see the reference for detail. 

Outline

What Is Electronic Packaging

       Four major functions: 

       Electronic package hierarchy: 

IC Trends and Packaging Technologies

 

       Since the invention of silicon integrated circuit (IC) in 1958, scale integration developed from small (SSI), medium (MSI), large (LSI), to very large (VLSI), ultra large (ULSI), giga (GSI), and other yet to come. The IC products are becoming smaller and smaller.

 

       On the other hand, the device density is becoming higher and higher. 50 years ago, every family has only 5 active electronic devices. A few years ago (1996~1997), this amount explosively increased to several millions with 0.35 mm lines. In the coming year, every family will own one billion transistors, and the lines are 0.18 mm.

  • PQFP: plastic quad flat package

  • TQFP: thin quad flat package

  • DCA: direct chip-attach package

  • CSP: chip scale package 

  • TCP: tape carrier package

  • PGA: pin grid array (PPGA, CPGA)

  • PBGA: plastic ball grid array

 

  • CBGA: ceramic ball grid array

  • TBGA: tape ball grid array

  • MBGA: metal ball grid array

  • Area Array Flip-Chip

Flip-Chip Packaging

       Theoretically, wafer scale integration (WSI), which builds the entire system or subsystems on a single wafer, is the most ideal electronic assembly. However, because of the poor yield of WSI, wafers are usually broken up into individual chips. These chips are then packaged on a substrate (chip on board) or in a carrier (either single-chip or multi-chip modules). There are at least three popular methods for interconnecting the chips on the substrate

       Among them, flip-chip provides the shortest possible leads, lowest inductance, highest frequency, best noise control, highest density, greatest number of I/Os, smallest device footprints, and lowest profile. The procedure includes 4 major steps: 

       Step 1, under bump metallurgy: 

       Step2, solder bump reflow: 

       Step3, flip-chip assembly: 

       Step 4, underfilling and curing: 

Electroless Redistribution for Flip-Chip

       Today (by stencil printing) pitches on wafers can be made to 200 mm or even 150 mm. But a pitch of 150 mm is already common for silicon circuits, and pitches below 100 mm are coming soon. This leads to the need for additional redistribution on top of dies, which convert the dense peripheral pad arrangement to an area array with relaxed pitch. 

       A example of redistributed chip. Here, peripheral pitch is the pitch on silicon circuits, while redistributed pitch is the pitch on wafers

       The procedure of electroless redistribution: 

 

Materials and Desired Properties

       Substrate (FR4, etc.): 

       Underfill and encapsulant (epoxies, silicones, polyimides, sycar, polyurethane, etc.): 

       Passivation (SiO2, polyimide, silicon nitride films, etc.): 

       Solder (Pb/Sn, etc.): 

       Chip (silicon, etc.): 

Problems and Challenges

       High on/off clock frequency vs. Radiated noise

       High system density vs. Lower power consumption

       Higher density and smaller package vs. Quickly heat diffusing

       Large thermal expansion mismatch vs. High mechanical reliablity

Reference

  1. J. Lau, C. Wong, J. Prince, and W. Nakayama, Electronic Packaging: Design, Materials, Process, and Reliability, McGraw-Hill.

  2. J. Lau, Flip Chip Technologies, McGraw-Hill.

  3. P. Coskina, M. Popper, K. Heinricht, A. Ostmann, E. Jung, J. Kloeser, R. Aschenbrenner, and H. Reichl, "Wafer Bumping for Wafer-Level CSP's and Flip Chips Using Stencil Printing Technology".

  4. A. Ostmann, Ch. Dombrowskr, R. Aschenbrenner, and H. Reichl, "Development of an Electroless Redistribution Process".

  5. M. Pecht, R. Agarwal, P. McCluskey, T. Dishongh, S. Javadpour, and R. Mahajan, 1999, Electronic Packaging Materials and Their Properties, CRC Press LLC, Florida.

  6. J. Lau and C. Chang, 1998, "Characterization of Underfill Materials for Functional Solder Bumped Flip chips on Board Application", Electronic Component and Technology Conference.