Introduction to Electronic Packaging
Yu Gu. Dept of Mechanical Engineering, SUNY at Stony Brook.
This web page is a rough summary to the background knowledge of electronic packaging. It is a course presentation by the author at April 2000 in Stony Brook University. Content include brief introductions on IC history, packaging technologies, flip-chip assembly, electroless redistribution, material properties, and challenges we faced. Many of the pictures are referred from other people's work. Please see the reference for detail.
Outline
What is electronic packaging?
IC trends and packaging technologies
Flip-chip packaging
Electroless redistribution for flip-chip
Materials and desired properties
Problems and Challenges
Reference
What Is Electronic Packaging
Four major functions:
Provide
a path for electronics current that powers the circuits on the chip
Distribute
the signals onto and off the IC chip
Remove
the heat generated by the circuits on the IC chip
Support
and protect the IC chip from the hostile environments
Electronic package hierarchy:
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0th-level
is chip-level packaging. For example, CSP
1st-level
is either single- or multi-chip modules
2nd-level
is from the 1st level to the printed circuit board (PCB)
3rd-level
is from the card to the motherboard
IC Trends and Packaging Technologies
Since the invention of silicon integrated circuit (IC) in 1958, scale integration developed from small (SSI), medium (MSI), large (LSI), to very large (VLSI), ultra large (ULSI), giga (GSI), and other yet to come. The IC products are becoming smaller and smaller. |
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On the other hand, the device density is becoming higher and higher. 50 years ago, every family has only 5 active electronic devices. A few years ago (1996~1997), this amount explosively increased to several millions with 0.35 mm lines. In the coming year, every family will own one billion transistors, and the lines are 0.18 mm. |
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Flip-Chip Packaging
Theoretically, wafer
scale integration (WSI), which builds the entire system or subsystems on a
single wafer, is the most ideal electronic assembly. However, because of the
poor yield of WSI, wafers are usually broken up into individual chips. These
chips are then packaged on a substrate (chip on board) or in a carrier (either
single-chip or multi-chip modules).
Face-up wire bonding
Face-up tape-automated bonding (tape lead)
Flip-chip packaging
Among them, flip-chip provides the shortest possible leads, lowest inductance, highest frequency, best noise control, highest density, greatest number of I/Os, smallest device footprints, and lowest profile. The procedure includes 4 major steps:
Step 1, under bump metallurgy:
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Step2, solder bump reflow:
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Step3, flip-chip assembly:
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Step 4, underfilling and curing:
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Electroless Redistribution for Flip-Chip
Today (by stencil printing) pitches on wafers can be made to 200 mm or even 150 mm. But a pitch of 150 mm is already common for silicon circuits, and pitches below 100 mm are coming soon. This leads to the need for additional redistribution on top of dies, which convert the dense peripheral pad arrangement to an area array with relaxed pitch.
A example of redistributed chip. Here, peripheral pitch is the pitch on silicon circuits, while redistributed pitch is the pitch on wafers:
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The procedure of electroless redistribution:
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Materials and Desired Properties
Substrate (FR4, etc.):
- low dielectric constant•
- low dissipation factor
- •high volume resistivity•
- high thermal conductivity
- •appropriate CTE•
- high thermal stability
- high chemical resistance
Underfill and encapsulant (epoxies, silicones, polyimides, sycar, polyurethane, etc.):
high glass transition temperature
good chemical resistance
low moisture absorption
low viscosity (fast flow)
good adhesion strength and high modulus
low curing temperature
suitable CTE
low dielectric constant
excellent thermal conductivity
low ionic contaminants
good UV-VIS and alpha particle protection
Passivation (SiO2, polyimide, silicon nitride films, etc.):
protect the metallization from environment
insulate the device on the silicon suface
Solder (Pb/Sn, etc.):
low reflow temperature
high shear strength
favorable fatigue properties
suitable CTE
Chip (silicon, etc.):
Problems and Challenges
High on/off clock frequency vs. Radiated noise
High system density vs. Lower power consumption
Higher density and smaller package vs. Quickly heat diffusing
Large thermal expansion mismatch vs. High mechanical reliablity
Reference
J.
Lau, C. Wong, J. Prince, and W. Nakayama, Electronic Packaging: Design, Materials, Process, and Reliability,
McGraw-Hill.
J.
Lau, Flip Chip Technologies,
McGraw-Hill.
P.
Coskina, M. Popper, K. Heinricht, A. Ostmann, E. Jung, J. Kloeser, R.
Aschenbrenner, and H. Reichl, "Wafer
Bumping for Wafer-Level CSP's and Flip Chips Using Stencil Printing
Technology".
A.
Ostmann, Ch. Dombrowskr, R. Aschenbrenner, and H. Reichl, "Development
of an Electroless Redistribution Process".
M.
Pecht, R. Agarwal, P. McCluskey, T. Dishongh, S. Javadpour, and R. Mahajan,
1999, Electronic Packaging Materials
and Their Properties, CRC Press LLC, Florida.
J.
Lau and C. Chang, 1998, "Characterization
of Underfill Materials for Functional Solder Bumped Flip chips on Board
Application", Electronic Component and Technology Conference.