All interrupt lines attached to the CPU are associated with a bit position in an interrupt register. If an interrupt on a line is generated, it will only be recognised by the CPU if the corresponding bit in the interrupt register is a 1. In order to allow the pattern of bits in the interrupt register to be changed, there is an associated register, the interrupt mask register, which is program addressable. This register is permanently ANDed with the interrupt register so that only if there is a 1 bit in the mask register can an interrupt on that line be recognised.

If a particular interrupt service routine wishes to inhibit interrupts of a lower priority, then at the beginning of the service routine it must load the interrupt mask register with an appropriate pattern of bits. Only those bit positions corresponding to interrupts that are to be allowed are set to 1, all other bits set to 0.