Like the 6502, the 6809 was based on the Motorola 6800 (1974), which was initially based on the design of the big endian DEC PDP-8, though the 6809 expanded the design significantly. The 6809 had two 8 bit accumulators (A & B) and could combine them into a single 16 bit register (D). It also featured two index registers (X & Y) and two stack pointers (S & U), which allowed for some very advanced addressing modes (The 6800 had A & B (and D) accumulators, one index register and one stack register). The 6809 was source compatible with the 6800, even though the 6800 had 78 instructions and the 6809 only had around 59. Some instructions were replaced by more general ones which the assembler would translate, and some were even replaced by addressing modes. While the 6800 and 6502 both had a fast 8 bit mode to address the first 256 bytes of RAM, the 6809 had an 8 bit Direct Page register to locate this fast address page anywhere in the 64K address space.
Other features were one of the first multiplication instructions of the time, 16 bit arithmetic, and a special fast interrupt. But it was also highly optimized, gaining up to five times the speed of the 6800 series CPU. Like the 6800, it included the undocumented HCF (Halt Catch Fire) bus test instruction (documented as $00 in the 68HC11, described below).
The 6800 and 6809, like the 6502 series, used a single clock cycle
(the base cycle, plus a cycle rotated 90 degrees out of phase) to generate the timing for
four internal execution stages, so that there were instructions which executed in one
external 'cycle' (this is different from clock-doubling, which uses a phase-locked-loop to
generate a faster internal clock which is synchronised with an external clock).
Most CPUs, such as the
Intel
8080,
used the external clock directly, so an equivalent instruction would take four cycles,
meaning a 2MHz 6809 would be roughly equivalent to a 8MHz
8080.
The 680x and 650x only accessed memory every other cycle,
allowing a peripheral (such as video, or even a second cpu)
to access the same memory without conflict.
Motorola later produced CPUs
in this line with a standard four-cycle clock.
The 6800 lived on as well, becoming the 6801/3, which included ROM, some RAM, a serial I/O port, and other goodies on the chip (as an embedded controller, minimizing part counts). The 6803 led to the 68HC05 and 68HC11 (two 8 bit or one 16 bit data register, two 16 bit index, and one 16 bit stack register, and an expanded instruction set with 16 bit multiply operations), the latter was extended to 16 bits as the 68HC16 (and a lower cost 16 bit 68HC12 (May 1996)). It remains a popular embedded processor, and radiation hardened versions of the 68HC11 have been used in communications satellites, but the 6809 was a faster and more flexible chip, particularly with the addition of the OS-9 operating system.
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A.T.Pon@cs.cf.ac.uk