Looking back, it was logical, since most 8 bit processors featured
direct 16 bit addressing without segments.
The 68000 had sixteen 32-bit registers, split into data and address
registers. One address register was reserved for the Stack Pointer.
Data registers could be used for any operation, including offset from
an address register, but not as the source of an address itself.
Operations on address registers were limited to move, add/subtract, or
load effective address.
Like the Z-8000,
the 68000 featured a supervisor and user mode (each with its own Stack
Pointer). The Z-8000
and 68000 were similar in
capabilities, but the 68000 was 32 bit units internally, making it
faster and eliminating forced segmentations. It was designed for
expansion, including specifications for floating point and string
operations (floating point was added in the 68040 (1991), with eight 80
bit floating point registers compatible with the 68881/2 coprocessors).
Like many other CPUs of the time, the 68000 could fetch the next
instruction during execution (a 2 stage pipeline).
The 68010 added virtual memory support (the 68000 couldn't restart
interrupted instructions) and a special loop mode - small
decrement-and-branch loops could be executed from the instruction
fetch buffer. The 68020 (1984) expanded external data and address bus
to 32 bits and added a 256 byte cache, while the 68030 brought the MMU
onto the chip (it supported two level pages (logical, physical) rather
than the segment/page mapping of the Intel
80386
and IBM
S/360
mainframe). The 68040 (1991) added fully cached
Harvard busses (4K(?)
each for data and instructions), 6 stage pipeline, and on chip FPU.
The 68060 (late 1994) expanded the design to a superscalar
version, like the Intel Pentium
and NS320xx (Swordfish) series before it.
Like the Nx586,
AMD K5,
and Intel's
"Pentium Pro",
the third stage of the 10-stage 68060 pipeline translates the 680x0 instructions to a
decoded RISC-like form (stored in a 16 entry buffer in stage four),
and uses resource renaming to
reorder instructions. There is
also a branch cache, and branches are folded into the decoded
instruction stream like the AT&T Hobbit and other more recent processors,
then dispatched to two pipelines (three stages: Decode, addr gen,
operand fetch) and finally to two of three execution units -
2 integer, 1 floating point) before reaching two 'writeback' stages.
Cache sizes are doubled over the 68040.
The 68060 also also includes many innovative power-saving features
(3.3V operation, execution unit pipelines could actually be shut down,
reducing power consumption at the expense of slower execution, and the
clock could be reduced to zero) so power use is lower than the 68040
(4-6 watts vs. 3.9-4.9). Another innovation is that
simple register-register instructions which don't generate addresses
may use the the address stage ALU to execute 2 cycles early.
The embedded market became the main market for the 680x0 series
after workstation venders (and the Apple Macintosh) turned to faster
RISC processors, so a variety of embedded versions were introduced.
Later, Motorola designed a successor called Coldfire (early 1995), in
which complex instructions and addressing modes (added to the 68020)
were removed and the instruction set was recoded,
simplifying it at the expense of compatibility (source only, not binary)
with the 680x0 line.
The Coldfire 52xx architecture resmbles a stripped (single pipeline)
68060,
The 5 stage pipeline is literally folded over itself - after two fetch
stages and a 12-byte buffer, instructions pass through the decode and
address generate stages, then loop back so the decode becomes the
operand fetch stage, and the address
generate becomes the execute stage (so only one ALU is required for
address and execution calculations). Simple (non-memory) instructions
don't need to loop back. There is no translator stage as in the 68060
because ACE instructions are already in RISC-like form. The earlier 51xx
version has a straight 68040-based 6 stage pipeline and includes 680x0
instructions (in user mode).
At a quarter the physical size and a fraction of the power
consumption, Coldfire is about as fast as a 68040 at the same clock rate,
but the smaller design allows a faster clock rate to be acheived.
Few people wonder why Apple chose the Motorola 68000 for the
Macintosh, while IBM's decision to use
Intel's 8088 for the
IBM PC has baffled many. It wasn't a
straightforward decision though. The
Apple Lisa was the predecessor to the Macintosh, and also used a 68000
(eventually - 8086
and slower bitslice
CPUs (which Steve Wozniak thought were neat) were initially considered
before the 68000 was available).
It also included a fully multitasking, GUI based operating system,
highly integrated software, high capacity (but incompatible) 'twiggy'
5 1/4" disk drives, and a large workstation-like monitor. It was better
than the Macintosh in almost every way, but was correspondingly more
expensive.
The Macintosh was to include the best features of the Lisa, but at
an affordable price - in fact the original Macintosh came with only 128K
of RAM and no expansion slots. Cost was such a factor that the 8 bit
Motorola 6809 was the original design choice, and
some prototypes were built, but they quickly realised that it didn't
have the power for a GUI based OS, and they used the Lisa's 68000,
borrowing some of the Lisa low level functions (such as graphics toolkit
routines) for the Macintosh.
The 68000 was actually a 32 bit architecture internally, but 16 bit
externally for packaging reasons (the 68008 version was reduced to 8
data bits and 20 address bits to lower costs, and the 68020 was 32 bits
externally). It also included 24 bit addressing, without the use of
segment registers. That meant that a single directly accessed array or
structure could be larger than 64K in size. Addresses were computed as
32 bit, but the top 8 bits were cut to fit the address bus into a 64
pin package (address and data shared a bus in the 40 pin packages of
the Intel
8086
and Z-8000),
and some programmers stored type tags in the upper 8 bits, which
caused compatibility problems when versions with full 32 bit addressing
came out. Lack of forced segments made programming the 68000
easier than some competing processors.
Back to Motorola - The Microprocessor
A.T.Pon@cs.cf.ac.uk