HORMAZD P. COMMISSARIAT
1200, Dale Avenue, # 76
Mountain View, CA 94040
Tel.No. (650)9649969 Pager# (415)9156749
e-mail: hcommiss@mipos2.intel.com
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EDUCATION: M.S. , Electrical Engineering, June 1995, G.P.A.: 3.84 / 4.00
Virginia Polytechnic Institute & State University,
Blacksburg, Virginia.
Thesis: Performance Modeling of Single and Multi-Processor Computer Architectures
running DSP (Digital Signal Processing) Algorithms. High-level VHDL (VHSIC
Hardware Description Language) models were used to model the components
of 4 types of computer architectures.
Courses Studied:
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Hardware Modeling with VHDL VLSI Design Technology
Advanced Computer Architecture Computer Networks and TCP/IP programming
Microprocessor System Design Advanced C/C++ for engineers
Digital Signal Processing Computer Aided Electronic Circuit Design
Digital and Analog Communications Microwave and Fiber Optic Technology
B.E. , Electronics Engineering, May 1992,
University of Bombay, Bombay, India. Class/Grade : FIRST CLASS (Honors)
GRADUATE: * Developed a VHDL Model of an Infra-Red Sensing and Tracking (IRST) Algorithm.
PROJECTS * Designed and implemented an Histogram Generator IC used in Image Processing.
* Developed a "Gopher" server and client in C using TCP/IP Programming.
* Cache Design using cache simulator DINERO III.
* Manufacture and Testing of Optical Fiber-Based Corrosion Sensors for Boeing Space
and Defense Group.
EXPERIENCE: * Senior Design Engineer, INTEL Corporation, Santa Clara Processor Division, Jun'95 - Present
VLSI Circuit Design for INTEL's next-generation IA-64 microprocessor (MERCED).
Responsible for Circuit Design of the Register Renaming Unit and Stacking Unit
and the Integer Execution Unit as well as some circuit design of the Floating
Point Unit. This involved Floorplanning, schematic design, verification, timing
analysis, reliability analysis, layout planning and supervision, HDL Code maintenance.
* Graduate Research Assistant, Computer Research Laboratory,
Virginia Polytechnic Institute and State University,(VPI&SU), Jan '94 - June'95
Rapid Prototyping of Application Specific Signal Processors using VHDL.
* Audio Visual Technician, Squires Student Center, Aug '93 - Dec '93
Virginia Polytechnic Institute and State University,(VPI&SU),
Installation and maintenance of various Audio Visual Equipment.
* Trainee Software Engineer, MASTEK (Management And Software Technology),
Bombay, Financial Accounting package on LAN using COBOL, Feb '93 - July'93
* Graduate Trainee Engineer, Godrej & Boyce Manufacturing, Company, Bombay,
Installation and maintenance of electrical & electronic equipment, May '92 - Dec '92
* Project Training at Dynalog Micro-Systems, Bombay, Implemented a P.I.D. Controller
using a 8097 Micro-controller with interfacing to a P.C., Aug '91 - May '92
COMPUTER: Languages VHDL, C, C++, HTML, Pascal, FORTRAN, COBOL, BASIC.
SKILLS Assembly languages for 8085, 8086, 8088, 8048, 8051, 8097.
CAD Tools Synopsys (VHDL Analyzer-Simulator-Debugger), MAGIC, SPICE, SPW,
MATLAB, Ilogix (Express VHDL), Cadence Schematic editor and
Circuit Simulator, Frameworks.
O.S. SUN-OS 4.1.3, UNIX System V , NOVELL-NETWARE, DOS.
PUBLICATION: 1. Developing Re-usable Performance Models for Rapid Evaluation of Computer
Architectures running DSP Algorithms. - H.P.Commissariat, Dr.F.G.Gray,
Dr.J.R.Armstrong, Dr.G.A.Frank. 2nd Annual RASSP Conference Proceedings,Fall'95.
OTHER : 1. Chairman, Virginia Tech, IEEE Computer Society.
ACTIVITIES 2. Vice Chairman, TSEC, IEEE Communications Society.
3. System Administrator, VTCOSY (An Internet Conferencing Host).
4. Editor, IEEE, TSEC branch's journal "DATABUS".
5. 1st place, IEEE student project contest.
6. Recipient, National Merit Scholarship.
REFERENCES: Available upon request.