module alhamdulillah(BCLK, reset_n, stcmp, quad_fill, CTRL_PINS, parallel_data, ERROR, 
				   packet_error, packet_good, push, fifo_mode, wenable, oenable, DATA_IR_out, 
				   ADDR_IR, DATA_IR_in, data_dec_out, CALC_CRC, DATA_F_C_D,broadcast); //, data_decode, dest_id);
input stcmp, quad_fill, BCLK, reset_n;
input [2:0]CTRL_PINS;
input [31:0]parallel_data;
input[15:0] DATA_IR_in;

wire reset_decoder, reset_crc;
output [31:0] CALC_CRC, DATA_F_C_D;
wire [31:0] CALC_CRC, DATA_F_C_D;

output [7:0] ADDR_IR;
wire [2:0]header_length;
wire [7:0]ADDR_IR_dec, ADDR_IR_Rx;
output ERROR, wenable, packet_error, packet_good, push, fifo_mode, oenable, broadcast;
output [15:0] DATA_IR_out;
output [3:0]data_dec_out;
//output [3:0]data_decode;
//output [15:0]dest_id;
receiver R11(    	   		 BCLK,
                             reset_n, 
                             decode_error, 
                             decode_complete, 
                             data_payload, 
                             stcmp,
                             quad_fill, //from parallel processable memory, available at negedge BCLK for single period
                             header_length,                             
                             CTRL_PINS,
                             CALC_CRC,
                             parallel_data, // from parallel process memory
			     			 			                                   
   							 ERROR,
							 decode,
							 reset_decoder_rx,
							 wenable,  // write signal to CSR
							 crc_in,
							 DATA_IR_out,
							 ADDR_IR_Rx,
							 DATA_F_C_D,
							 packet_error,
							 packet_good,
							 push,
							 fifo_mode, // set fifo mode for reception
							 reset_rx);
							 
decoder D1(
                     BCLK,
                     decode,
		     		 /*receive_or_transmit*/ 0,
		     		 reset_decoder,                     
           	     	 DATA_IR_in, 
		             DATA_F_C_D,
                     data_payload,
                     header_length,
                     decode_error,
                     decode_complete,
                     ADDR_IR_dec,
                     oenable, data_dec_out, broadcast); 
crc C1( 	//Inputs
			reset_crc, 
			BCLK, 
			DATA_F_C_D,
			crc_in, 
			//Outputs
			CALC_CRC);

assign reset_decoder = reset_decoder_rx & reset_n;
assign reset_crc = reset_n & (~ reset_rx);
assign ADDR_IR = oenable ? ADDR_IR_dec : ADDR_IR_Rx;

endmodule