module mashallah ( BCLK, SCLK, reset_n, strobe, packet_error, data_end,ERROR, 
				   broadcast, monitor, Req_Type, D, reception, lreq, RE, stcmp, 
				   quad_fill, Q, ctrl_pins, ctl);

input BCLK, SCLK, reset_n, strobe, packet_error, data_end, broadcast,ERROR;
input [0:16]Req_Type;
input [2:0]monitor;
inout [1:0] ctl;
input [7:0] D;
output RE, stcmp, reception, lreq, quad_fill;
output [31:0] Q;
output [2:0]ctrl_pins;



PLI P1    ( BCLK, SCLK, RE, stcmp, pipe_en, reception, lreq,  ctrl_pins, reset_n, strobe,ERROR, 
	        packet_error, data_end, broadcast, monitor, Req_Type, ctl, D);

Q_ASSM Q1 ( BCLK, SCLK, D, reset_n, pipe_en, quad_fill, ctl, Q );


endmodule