How to have 4 Mb on a G
compiled by Philippe Teuwen
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Version 0.02 26th November 1996
! This document is given only for information
and *NOTHING WAS TESTED* , so ANY WARRANTY !
Remember: you need the HC00, HC174 and resistors for enabling port 2.
See other docs to know how to do that.
512k SRAM
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D3 -| D3 GND |- GND * : different from a 128k
D4 -| D4 D2 |- D2 so you can solder all
D5 -| D5 D1 |- D1 the pins on the main RAM
D6 -| D6 D0 |- D0 or a 128k port 1 excepted
D7 -| D7 A0 |- A0 these 3 ones.
* NCEn -| NCE A1 |- A1 All the pins are common for
A10 -| A10 A2 |- A2 all the 512k excepted the NCEn
GND -| NOE A3 |- A3
A11 -| A11 A4 |- A4
A9 -| A9 A5 |- A5
A8 -| A8 A6 |- A6
A13 -| A13 A7 |- A7
NWE -| NWE A12 |- A12
* A17 -| A17 A14 |- A14
A15 -| A15 A16 |- A16
Vcc -| Vcc A18 |- A18 *
32 ----/^\---- 1
Just one 512k chip
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NCEn to pin 6 or 10 of HC00 ( =N(BEN*N(AR18)) or =NCE2.2 )
Now HC00 must be powered all the time: disconnect pins 1 and 14
and wire them to Vcc (as pin 32 of main RAM)
Because if HC00 is turned off, the 512k will be turned on.
8*512k chips (->4Mb)
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Must use a decoder:
74HC138: 3-line-to-8-line decoder/demultiplexer (with lines inverted)
1 ----\_/----
A19 -| A Vcc |- Vcc Connect NCEn of SRAMs 512k
A20 -| B Y0 |- NCE5.0 respectively to NCE5.n
A21 -| C Y1 |- NCE5.1 (n=0-7)
GND -| NG2A Y2 |- NCE5.2
GND -| NG2B Y3 |- NCE5.3 Rem: CE2.2 = BEN*N(AR18)
CE2.2 -| G1 Y4 |- NCE5.4
NCE5.7 -| Y7 Y5 |- NCE5.5
GND -| GND Y6 |- NCE5.6
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G1 G2* C B A | Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 G2* = G2A+G2B
-------------|------------------------
X H X X X | H H H H H H H H
L X X X X | H H H H H H H H
H L L L L | L H H H H H H H
H L L L H | H L H H H H H H
H L L H L | H H L H H H H H
H L L H H | H H H L H H H H
H L H L L | H H H H L H H H
H L H L H | H H H H H L H H
H L H H L | H H H H H H L H
H L H H H | H H H H H H H L
Thanks to:
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Stefano Garavaglia for a judicious remark
(alter.ego@iol.it) about powering the chips
Contacting the author
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Philippe TEUWEN
Belgium
s952365@student.ulg.ac.be