Digital Electronic Principles

What is the 2⿿s complement of the binary number 100000002?
1. 01
2. 01111111
3. 1
4. 10000000
Decimal equivalent of Hexadecimal number AF is
1. 1015
2. 1315
3. 110
4. 175
The decimal equivalent of binary number 101.1012 is
1. 5.3
2. 5.101
3. 5.5
4. 5.625
What is the BCD code of the decimal number 97 ?
1. 10010111
2. 10010001
3. 10100001
4. 01001111
Add the two binary numbers of 1011 and 110.
1. 10111
2. 10001
3. 11111
4. 01101
The binary equivalent of decimal 12.5 is
1. 111.1
2. 101.1
3. 1100.11
4. 1100.1
The hexadecimal equivalent of decimal number 255 is
1. EF
2. FF
3. 2F
4. F2
Convert 10010.01 to a decimal number.
1. 17.125
2. 11.5
3. 16.625
4. 18.25
The decimal number 34 when converted to binary is
1. 100001
2. 111101
3. 111011
4. 100010
10001001.0011BCD is equivalent to decimal
1. 111.3
2. 89.3
3. 137.185
4. 19.3
The Hexadecimal result of 102 + 1010 is
1. 10
2. C
3. 20
4. 12
What is the largest decimal value that can be represented by an 4-bit binary number?
1. 15
2. 16
3. 32
4. 8
The binary result of 2410 + 4510 is
1. 1010101
2. 100101
3. 110101
4. 1000101
The result of 1101 - 0110 is
1. 0101
2. 0111
3. 1000
4. 1001
The decimal equivalent of the octal number 17 is
1. 10001
2. 8
3. 87
4. 15
The circuit represents a/an
1. NAND gate
2. AND gate
3. NOR gate
4. OR gate
Complete the above table for the even parity bit
1. 100110
2. 000111
3. 111000
4. 001001
The two inputs to an XOR gate are 1001001 and 1111111. The output is
1. 0110110
2. 1100110
3. 1001001
4. 0100100
What is the logic function for the truth table shown?
1. AND function.
2. XOR function.
3. NAND function.
4. XNOR function.
The logic circuit in the figure above is equivalent to a/an
1. NOR gate
2. OR gate
3. AND gate
4. NAND gate
If both inputs of a NOR gate are connected together, it will function as a/an
1. NOT gate.
2. NAND gate.
3. AND gate.
4. OR gate.
The function of a NOR gate is the same as a/an
1. NOT gate with another NOT at its output
2. OR gate with an inverter at its output
3. NAND gate with an inverter at each of its inputs
4. OR gate with an inverter at each of its inputs
If both the inputs of a NAND gate are connected together, it will function as a/an
1. NAND gate
2. AND gate
3. NOT gate
4. OR gate
An XOR gate can be used in a/an
1. one-bit memory circuit
2. up-counter circuit
3. down-counter circuit
4. parity bit checking circuit
The two inputs to an XNOR gate are 1001001 and 1111111. The output is
1. 0100100
2. 1001001
3. 0110011
4. 1100110
The two inputs to an XOR gate are 1001001 and 1111111. The output is
1. 0100100
2. 1001001
3. 0110011
4. 1100110
If one of the input is X and other input is zero, the output of a 2-input AND will be
1. 2
2. X
3. 0
4. 1
The truth table shown is a/an
1. XOR gate
2. XNOR gate
3. AND gate
4. NAND gate
The numbers of combination in the truth table of 2-input NAND gate are
1. 6
2. 4
3. 8
4. 2
The symbol represents a/an
1. NOR gate
2. Exculsive-OR gate
3. Exculsive-NOR gate
4. NAND gate
The output of an AND gate is high when all the inputs are at the
1. logic 0 level
2. half level
3. logic 1 level
4. complementary level
Name the symbol of the gate shown.
1. XOR gate.
2. XNOR gate.
3. OR gate.
4. NOR gate.
Figure above shows a truth table of a/an
1. OR gate
2. NOR gate
3. NAND gate
4. XNOR gate
The 2-input XOR gate will have a low output only when the two inputs bits are
1. high
2. low
3. same
4. different
Simplified Boolean expression from the the Karnaugh Map shown is
The simplified Boolean expression for the Karnaugh map shown is
The simplified Boolean expression for the Karnaugh map shown is
Which one of the following expressions is correct using DeMorgan's Theorem?
The simplified logic expression of the given circuit is
The simplified logic expression of the given circuit is
The simplified logic expression of the circuit shown is
1. 0
2. 1
The simplified output logic expression of the logic circuit shown is
4. A + B
Which of the following unsimplified Boolean equation for Y in the given truth table?
Using DeMorgan⿿s Theorem, simplify the given expression.
Which of the following unsimplified Boolean equation for Y in the given truth table?
The simplified logic expression of the given circuit is
1. AB
2. AC
3. B
4. A
Simplify the given logic expression
1. Z = 1
Simplify the following Boolean expression.
1. Y = A + B
4. Y = C
The simplified expression of the given expression is
The simplified Boolean expression for the Karnaugh map shown is
2. Y = D
4. Y = CD
LCD is unique because
1. it does not emit light.
2. it is easily multiplexed.
3. it requires a highly regulated dc drive voltage.
4. it consumes a large amount of power.
To protect a LED from excessive current, one should
1. use a series resistor.
2. reverse bias the diode.
3. use a parallel resistor.
4. use a forward voltage of 2V.
Which of these diagrams shows the standard notation for a seven-segment display?
The dot matrix display is commonly used because it
1. is simple to connect.
2. can display most characters.
3. is very cheap.
4. has good contrast and wide angle.
Refer to the diagram. which of the following LEDs will light up?
1. X and Y.
2. Y and Z
3. Y only
4. X and Z
Most LEDs are connected with series resistor to
1. reduce power.
2. reduce voltage.
3. adjust brightness.
4. limit current.
Which one of the following segments have to be lighted up to display the number 3 of a 7-segment LED display unit?
1. a,b,c and e.
2. a,b,d and e.
3. a,b,c,d and g.
4. a,b,c and d.
Which of the following 7-segment displays is correctly labelled?
Which of the following letter cannot be displayed by the 7-segment LED display?
1. U
2. B
3. P
4. E
An advantage offered by LED is
1. short operating life.
2. long operating life.
3. no light is emitted.
4. high power dissipation.
Which of the following displays should not be used in a room with very poor lighting?
1. Vacuum fluorescent display.
2. Incandescent display.
3. LED
4. LCD.
Refer to figure. The lighted segments are
1. b,c,f and g.
2. a,b,f and g.
3. b,c,e and f.
4. a,b,e and f.
In the 7-segment LED, light is emitted from the LED when the diodes are
1. forward biased.
2. connected together.
3. disconnected.
4. reverse biased.
What type of display unit is not a light source but absorbs and controls light?
1. Fluorescent light.
2. Dot matrix.
3. LCD.
4. LED
A common anode 7-segment LED has all 7 segments on. If each segment draws 5 mA, what is the current drawn from the supply?
1. 5 mA.
2. 10 mA.
3. 7 mA.
4. 35 mA.
The diagram shows the layout of a common anode LED 7-segment display. In use, for current limiting purpose, resistors are connected to terminals
1. H only.
2. A, B, C, D, E, F, G
3. A, C, E, G
4. A, B, C, D, E, F, G, H
Refer to the figure. Which of the following switches should be closed for the number "3" to appear?
1. 1,2,3,5 and 7.
2. 1,2,3,5 and 6.
3. 1,2,3,4 and 7.
4. 1,2,3,4 and 6
The word "font" in display means
1. display format.
2. segmented display.
3. display unit.
4. dot matrix display
Refer to figure. The CMOS can be interfaced to the TTL by
1. a TTL open-collector buffer.
2. a pull-up resistor.
3. a CMOS non-inverting buffer.
4. an inverter
A CMOS integrated circuit is characterised by
1. high noise immunity and low power dissipation.
2. low noise immunity and low power dissipation.
3. low noise immunity and high power dissipation.
4. high noise immunity and high power dissipation
To prevent damage to the CMOS IC chips, the chips are stored in
1. a plastic container.
2. a wooden container.
3. a conductive container.
4. oil
All unused CMOS inputs must be
1. connected to a TTL output.
2. left unconnected.
3. connected to the output.
4. connected to ground or Vcc
MSI in IC terminology stands for
1. medium scale interest.
2. manufacturer specified integration.
3. medium speed integration.
4. medium scale integration.
CMOS ICs as compared to TTL ICs, consume very little
1. signal
2. decibel
3. voltage
4. power
The average propagation delay of a standard TTL circuit is
1. 9 ns.
2. 2 ns.
3. 1 ns.
4. 20 ns.
An advantage of CMOS circuit is its
1. low fan out.
2. high speed.
3. low input resistance.
4. low power dissipation
When a CMOS gate drives a TTL gate directly without a buffer, the problem arise at the
1. low state.
2. high to low state.
3. low to high state.
4. high state.
When a TTL IC is used to drive a CMOS IC, a pull up resistor is used to
1. raise the TTL "high' output to +5V.
2. decrease the TTL 'low' output to 0V.
3. raise the TTL 'high' output to +3V.
4. maintain a constant output.
The power supply voltage range of a CMOS circuit is
1. +3V to +20V.
2. +3V to +5V.
3. +3V to +10V.
4. +3V to +15V.
The disadvantage of CMOS over TTL is that it
1. presents load on the driving device.
2. is slower.
3. has more flexibility in the supply voltages.
4. dissipates less power.
When compared to an equivalent discrete component circuit, the integrated circuit (IC) is
1. smaller, more reliable and consumes less power.
2. smaller, more reliable but consumes more power.
3. more reliable and consumes less power but operates at slower speed.
4. smaller, consumes less power but is less reliable.
The most significant advantage of CMOS digital ICs as compared to TTL digital ICs is their
1. low power dissipation.
2. excellent noise immunity.
3. low voltage rating.
4. fast propagation delay.
The TTL sub-family which combines the advantages of speed and lower power dissipation is
1. 74LS00
2. 74L00
3. 74H00
4. 74S00
The 74S00 series has the highest speed available in the TTL series. The device which is connected as a clamp from the base to collector of all the transistors in this series is the
1. resistor
2. capacitor
3. shockley diode.
4. schottky barrier diode
The power supply voltage for a TTL is
1. 10V.
2. 15V.
3. 20V.
4. 5V.
In the CMOS family, the dynamic power consumption will increase proportionately with the increase in operating
1. current
2. temperature.
3. frequency
4. voltage
Refer to figure. The figure shown is equivalent to
1. RS flip-flop.
2. D-type flip-flop.
3. T-type flip-flop.
4. clocked RS flip-flop.
In the NAND gate RS flip-flop, which of the following S and R inputs are prohibited?
1. S = 1, R = 0.
2. S = 0, R = 1.
3. S = 1, R = 1.
4. S = 0, R = 0.
The number of flip-flops required to store the binary equivalent of the decimal number 12 in a shift register is
1. 8
2. 4
3. 2
4. 16
How many bits of binary data can a single flip-flop store?
1. 1
2. 2
3. 3
4. 4
The trailing edge of a logic signal generally refers to its transiton from
1. 1 to 0.
2. A to B.
3. 0 to 1.
4. one level to the next.
Flip-flops that require clock pulses for triggering are known as the
1. symmetrical type.
2. synchronous type.
3. asynchronous type.
4. asymmetrical type.
Refer to figure. What type of clock pulse must be applied to trigger the flip-flop?
1. A logic high clock pulse.
2. A logic low clock pulse.
3. A low-to-high transition.
4. A high-to-low transition
For a clocked RS flip-flop, the flip-flop will not change states when a signal is not applied to the
1. J-K input.
2. Clock input.
3. Reset input.
4. Set input.
Refer to figure. It shows the symbol of a
1. positive-level triggered RS flip-flop.
2. negative-level RS flip-flop.
3. negative edge triggered RS flip-flop.
4. positive edge triggered RS flip-flop
D flip-flops are widely used in digital systems such as
1. toggle flip-flops.
2. binary counters.
3. shift registers.
4. decoders.
A JK flip-flop can be used individually to divide the clock input frequency by a factor of
1. 2
2. 4
3. 8
4. 16
A flip-flop is also known as
1. a Bistable multivibrator.
2. a Schmitt trigger.
3. a Monostable multivibrator.
4. an Astable multivibrator.
A group of flip-flops that is used to store a binary word is called a
1. truth table.
2. decoder.
3. register
4. multiplexer.
Refer to figure. The flip-flop shown will trigger only
1. on the low level of the clock pulse.
2. on the negative edge of the clock pulse.
3. on the high level of the clock pulse.
4. on the positive edge of the clock pulse
Refer to figure. It shows a NAND gate RS flip-flop. If the S and R inputs are set to "0", the flip-flopwill be in a
1. set state.
2. holding state.
3. forbidden state.
4. reset state
Refer to figure. To trigger the clock of the flip-flop, a
1. logic low is required.
2. logic high is required.
3. high-to-low transistion clocked pulse is required.
4. low-to-high transistion clocked pulse is required.
The J and K inputs to a JK flip-flop is 1,1. What is the output state when the clock is active?
1. Reset state.
2. Toggle state.
3. Prohibited state.
4. Set state.
The RS fli-flop wired in this figure is equivalent to the
1. T flip-flop.
2. J-K flip-flop.
3. D flip-flop.
4. J-K master-slave flip-flop.
Refer to figure. The frequency of the signal at point Z is
1. 7 KHz.
2. 70 KHz.
3. 28 KHz.
4. 1294 KHz.
An 8 MHz square wave drives a 4-bit binary counter. What is the frequency of the waveform at the output of the last flip-flop of the counter?
1. 1 MHz.
2. 500 KHz.
3. 1.6 MHz.
4. 250 KHz.
Flip-flops are used in registers because of their data
1. reset capability.
2. shift capability.
3. set capability.
4. hold capability.
What is the minimum number of JK flip-flops required to wire up a MOD-16 up-counter?
1. 2
2. 4
3. 8
4. 16
The figure shows a
1. Synchronous down-counter.
2. Asynchronous down-counter.
3. Asynchronous up-counter.
4. Synchronous up-counter.
If it is desired to have a ripple counter capable of attaining a maximum decimal count of 63. What is the minimum number of flip-flops required?
1. 5
2. 6
3. 7
4. 8
How many flip-flops will be required to store the binary equivalent of the decimal 10 in a serial shift register?
1. 1
2. 2
3. 4
4. 8
The number of flip-flops required to store the binary equivalent of the decimal number 12 in a shift register is
1. 2
2. 4
3. 8
4. 16
How many flip-flops are required to store one BCD digit of data?
1. 2 flip-flops.
2. 1 flip-flop.
3. 8 flip-flops.
4. 4 flip-flops
In a register employing serial transfer, how many clock pulses are required to complete a transfer of 8 bits of information?
1. 1
2. 2
3. 4
4. 8
A 4-bit asynchronous up-counter is in the 0111 state. If a series of ten pulses is entered at the input, what is the new output state?
1. 1111
2. 0001
3. 1110
4. 0010
A 4-bit binary counter has a clock frequency of 320KHz. What is the output frequency of the last flip-flop?
1. 20 KHz.
2. 80 KHz.
3. 40 KHz.
4. 160 KHz
A 4-bit ripple up counter begins in the 0000 state. What will be the state of the counter after one hundred pulse input?
1. 0100
2. 0001
3. 1100
4. 0000
Refer to figure. When all the J and K inputs of the flip-flops are connected to logic high, the circuit functions as
1. a synchronous up counter.
2. an asynchronous down counter.
3. an asynchronous up counter.
4. a synchronous down counter
To write a digital word into a parallel operated 8-bit storage register would require
1. 1 clock pulse.
2. 2 clock pulses.
3. 8 clock pulses.
4. 4 clock pulses
What is the maximum count for a counter using 3 flip-flops to perform binary counting?
1. 3
2. 6
3. 7
4. 8
The hexidecimal data stored in a 4-bit shift register is C. What will be its new content if the data is shifted to the left by one position?
1. F
2. 5
3. 4
4. 8
The number of flip-flops required to store the binary equivalent of the decimal number 12 in a shift register is
1. 2
2. 4
3. 8
4. 16
Refer to figure. After how many clock pulses will the entire contents of A-register be transferred to B-register?
1. 1 clock pulse.
2. 2 clock pulses.
3. 4 clock pulses.
4. 3 clock pulses.
To write a digital word into a parallel operated 8-bit storage register would require
1. 4 clock pulses.
2. 2 clock pulses.
3. 8 clock pulses.
4. 1 clock pulses.

Digital Electronic Principles

Test (Part 1)