CS -12 : COMPUTER ARCHITECTURE DEC 1998
 

Time : 2 Hours

Max. Marks : 75

 

Note : Question 1 is compulsory and carries 30 marks Attempt any three from the rest.
 

1. (a)

Explain in brief how instruction set, compiler technology, cache and memory hierarchy and CPU implementation affect the CPU perform and justify the effects in terms of program length, clock rate and effective CPI (cycles per instruction).

  (b) Analyze the data dependence among the following statements in a given program fragment :
 
Load R1, M(100) /R1M(100)/
Load R2, M(104) /R2 M(104)/
MULT R1, R2 /R1 (R1)x(R2)/
INC R1 /R1(R1) + 1/
STORE M(110),R1 /M(110)(R1)/
  (c) What are the limitations of conventional UNIX for parallel processing systems ?
  (d) Compare and contrast the characteristics of direct associative and sector caches.
  (e) Discuss the architecture environment for a Multi-threaded computer model.
  (f) what is m-way memory interleaving ?  Discuss the c-access memory scheme.
2.   Discuss the following terms in the context of  computer architecture :
  (a) Systolic arrays
  (b) Multiprocessing requirements at processor level
  (c) Scalability
  (d) Cross bar switch
  (e) VLIW architecture
3. (a) What are the differences between static and dynamic dataflow computers ?
  (b) Compare and contrast the central and distributed bus arbitration schemes.
  (c) What is multivector computing ?  How is it useful for supercomputers ?
4. (a) What are the different types of vector instructions ?  Discuss.
  (b) What is meant by Cache-Only Memory Architecture (COMA) model ?  How is it different from non-uniform-memory-access model ?
  (c) What is meant by hierarchical bus system for multiprocessing systems ?
5.   Write short notes on the following in the context of computer architecture :
    (i)   Multifunctional pipelines
(ii)  Monitors
(iii) Multicomputers
(iv) Clock rate, MIPS rate and throughtput
(v)  Branch handling in instruction pipeline
6.   Discuss the following in the context of parallel languages and compilers :
    (i)   Parallel code generation
(ii)  Parallel flow control
(iii) Parallel arrays
(iv) Synchronisation and communication features needed in parallel languages
(v)  Process management features needed for parallel languages.