Page Updated 21st April 2005
Mayuresh M. Rajwadkar
- Objective:
- Experience:
Current
employer: Sep 1999 to
Current [San Jose, CA, US]
Worked on four products for current employer in the fields of:
Worked on four products for current employer in the fields of:
- Timing driven physical ASIC Design, using Synopsys Astro, Physical Compiler and Cadence SOC Encounter
- Familiar with Astro/Apollo Milkyway database related tools,
scheme, make
- programming for P&R flow automation and debug.
- Experienced in Hercules LVS,DRC verification, knowledge of
runset coding and debug, StarRC-XT extraction.
- Familiar with TSMC 0.18um and 0.13um technologies and related IP from TSMC, Artisan, etc.
- Worked on IR drop and power EM assessment tools from Cadence/Simplex and Synplicity.
- Experience with SPICE simulation for chip IO SSO requirements, and detailed timing verification.
- Basic knowledge of RTL coding in Verilog, integrated a small Memory Bist logic into one of the products.
- Worked with Synopsys powrmill,timemill and railmill tools.
- Worked on Celtic,Celtic-NDC for SI analysis of two products.
- Front end library development
- Front end library modeling, for propritery formats, and IKOS modeling.
-
Master of Technology (Microelectronics) [Feb. 1998]
Indian Institute of Technology, Bombay.
-
Master of Science (Physics) [July 1996]
Indian Institute of Technology, Bombay.
-
Bachelor of Science (Physics) [April 1994]
Unversity of Bombay.
- Tools and Packages:
- Synopsys: Astro/Apollo/Milkyway, Physical Compiler, Hercules, Powermill/Timemill/Nanosim, HSPICE, StarRC-XT
- Cadence: Voltage Storm, Celtic/Celtic-NDC, LDV/NCSim, SOC Encounter
- Synplicity: Fortify
- Worked extensively with gnu-make, perl, bash,tcsh shell scripts. Familiar with Tcl/Tk
- Can relocate to any location/country
Available on request
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