About this Document The document is by : Shashwat Pandey
About this Document The following document is an introduction to switching on ATM networks. The document includes a general introduction to the ATM switch element, its requirements and performance issues. Several queueing methods, which aim to allow the switch to achieve the requirements are discussed. The Knockout switch element is introduced as an example of switch element architecture.
Why ATM? The bandwidth requirements for data traffic within commercial organizations have been increasing steadily for some time, both in the local area networks and in the wide area networks. Workstations have been used to introduce multimedia applications to the desktop, including components of voice, video and image, besides growing amounts of data. This development requires networks of greater bandwidth than commonly present today with the capability of handling multiservice traffic on the same network.
The asynchronous transfer mode (ATM) is being developed as a high speed networking technique for public networks capable of supporting many classes of traffic. ATM also uses the advantage of the new VLSI and fiber optic techniques recently developed.
ATM is a high-speed, packet-switching technique that uses short fixed length packets called cells. Fixed length cells simplify the design of an ATM switch at the high switching speeds involved. The selection of a short fixed length cell reduces the delay and most significantly the jitter (variance of delay) for delay-sensitive services such as voice and video. ATM is capable of supporting a wide range of traffic types such as voice, video, image and various data traffic.
In the following document I will introduce the basis of switching requirements in ATM broadband networks and introduce ATM switching solutions.
Introduction to ATM Switching Various switching architectures were developed in the past for different application such as voice and data, based on modes like STM (Synchronous Transfer Mode) and packet switching.
The switching architectures that were previously developed for STM and for conventional packet switching like X.25 are not directly applicable for broadband ATM.
Three major factors have a large impact on the implementation of the ATM switching architecture:
The ATM cell has a fixed length (of 48 bytes) payload and a fixed length header (5 bytes) with limited header functionality allow to implementation of different optimal switching architectures, queueing functions for example. Some of the switching techniques have been realized, or are in stage of implementation.
A growing number of ATM switches are commercially available and installed by public operations to offer a public, wide are a broadband service, sometimes called ATM Central Office. Other switches are deployed by private users and are used in an internal high speed telecommunication needs, often called ATM LAN.
Transport vs. Control In the description of ATM switching in the following introduction the attention will be paid to the "transport" part of the switch and not to the "control" part.
The transport network is defined as all the physical means which are responsible to the current transportation of the information from the ATM inlet to the ATM outlet. The transport network in the ATM network mainly performs functions located in the user plan of the ATM protocol reference model.
The control part of the switch is that which controls the transport network. It decide for instance, which inlet to connect to which outlet. The decision is based on incoming signaling information. The control network mainly performs functions located in the control plane of the ATM protocol reference model. The qulity of service parameters for the transport network are the cell loss rate, the error rate, cell delay and cell jitter .
ATM Switch Functions ATM is connection oriented. All cells belong to a virtual connection pre-established by the . All traffic is segmented into cells for transmission across the network. The sequence integrity of all the cells in the virtual connection is preserved across each ATM switch to simplify reconstruction of the original traffic at the destination (allows smaller total delay on the net). The ATM cell is 53 bytes long, built of 48 payload bytes and a 5 bytes header. Each cell's header contain a VCI (virtual channel identifier) that identifies the virtual connection to which the cell belongs.
The ATM switch has several main tasks:
In order to provide the switching function, both physical and logical identifiers of the incoming cell have to be related to physical and logical identifiers of the outgoing cell. Two functions have to be implemented in the ATM switching system.
The first function is the space switching function. The space switching function is the one which allows the connection between every input and every output. An important aspect of space switching is the internal routing. This means how the information is routed internally in the switch. The internal structure of the switch must allow connections between every input to every output.
The second function is time switching. Since ATM is working in an asynchronous mode, cells which had arrived in various time slots from the different inputs can be delivered from different outputs in different time slots (there is no time identifier in ATM as it is in STM). Since there is no pre-assigned time slot connection, a contention problem arises if more than two logical channels are connected to the same output at the same time slot. This problem in the ATM switch is solved by implementing a queueing function in the ATM switch system.
In this work the functions of routing and queueing will be discussed in more detail.
General Structure of an ATM switchThe ATM switch has to handle a minimum of several hundred thousand cells in a second at every switch port. A switch has to connect from a few ports to thousands of ports. In principle, a switch fabric can be implemented by a single switching element. But from practical reasons the switch fabric has to be built of basic switching building blocks - .
A switching element is the basic unit of the switch fabric. It can be implemented in a single integrated circuit element. At the input port (inlet) the routing information of the incoming cell is analyzed and the cell is then directed to the correct output port (outlet). In general the switching element consists of an interconnection network , and IC (input controller) for each incoming line and an OC (output controller) for each outgoing line. Arriving cells will be synchronized to the internal clock by the IC. The OC transport cells which have been received from the interconnection network toward the destination. The IC and OC are coupled by the interconnection network.
There are several switch element requirements to perform the switch functionality . A general structure of a switching element is in the figure below :
General model of switching element
Switching Element RequirementsAn ATM network has to support a wide range of applications using various kinds of information in, a wide range of speeds from telecontrol to high quality video. These services define different requirements in terms of bit rate, behavior in time (constant bit rate or variable bit rate), semantic transparency (cell loss rate, bit error rate) and time transmission (over all delay, jitter). The ATM switch architectures have to be considered in these requirements.
Performance Since ATM is defined to be connection oriented, after connection set-up a logical connection must be found between the logical inlet and the logical outlet.
Connection blocking is defined as the probability that not enough resources can be found to allow all the required physical connections between inlets and outlets at any time.
In an ATM switch it is possible that temporarily too many cells in the switch have to be transmitted through the same link (switch internal or external link). In optimal operational conditions there is an available entry in a queue to hold all the cells. But if the queue is currently full, another cell that will require the same queue will be lost.
The probability of a cell lost mast be kept in a specified limits to assure high semantic transparency. Typical values for cell loss in ATM are in the range of 10^(-8) to 10^(-10).
Some switching architectures are designed such that they will not suffer from cells competing for the same resources internally, but only at their inlets and/or outlets.
It is also possible that from some internal routing error a cell will be sent to the wrong logical connection. If such an error occurs, error impact is doubled by the fact that one destination will miss a cell and that a second destination will accept an additional cell. The switch element has to be designed so that cell insertion error probability will be about 1000 times better than a cell loss.
To allow support of different real time services in an ATM network, a maximal delay has to be guaranteed and a low values of jitter.
Typical delay values are between 10 and 1000 usec, with jitter of 100 nsec or less. The delay and the jitter in the cell are strongly related to the queueing in the switching element. A small queue will assure better delays but will increase the cell loss probability.
Information RatesA large number of information rates have to be switched in the same ATM switch. The maximal bit rate which a future ATM switch has to be able to switch lies around 150 Mbit/sec. For such fast services, the switching element can be implemented as several switching elements in parallel. Or, several 150Mbit/sec switching elements can be multiplexed on a single link. That will require a switching rate in the order of Gbit/sec.
BroadcastIn classical connection oriented packet switching services, only point to point connections are available, because the information (cell) can be switched from one logical inlet to one logical outlet only. In future broadband networks broadcast and multicast services are required for different applications from electronic-mail to network TV services.
Queueing MethodsThere are many queueing problems in an ATM switch because actually the ATM switch performs statistical multiplexing in the switch inputs and de-multiplexing in the switch outputs. Suppose two ATM cells arrived at two inlets at the same time and are aiming for the same outlet. Some arbitration mechanism and queue of waiting cells has to be implemented in the switch. There are several queueing possibilities. It is possible to add a queue at the switch element inputs, add a queue at the switch output, or add a queue between the inputs on the outputs of the switch.
The different possibilities are described briefly.
Input Buffers In this configuration the buffers are located at the input controller (IC). When using a first-in-first-out (FIFO) buffer, a collision occurs if two or more head-of-the-queue cells compete simultaneously for the same output. Then all but one of the cells are blocked. The cells behind the blocking head-of-the-queue cell are also blocked even if they are destined for another available (currently not in use) output. In this method the switch interconnection network will transfer the the cell from the input buffer to the output buffer without internal conditions. Arbitration logic is needed to determine which of the cells held in different inlet buffers destined to the same output will be transferred in the interconnection network. The arbitration logic can be from very simple logic (e.g. simple round robin) to more complex arbitration methods (aiming to keep the same queue length in all the buffers).
To overcome this disadvantage, the FIFO buffer can be replaced by a random access memory (RAM). If the first cell in the queue is blocked, the next cell which is destined for an idle output (or internal switch interconnection network link) will be selected for transmission. The disadvantage of this solution is that a complex buffering control is required to find a cell destined to an idle connection and also to guarantee a correct cell sequence of cells destined for the same output.
The input buffer approach achieves the worst performance in the sense of the queue length required to achieve a given cell-loss rate in various switch loads in comparison to the other two queueing methods.
Input Buffering.
Output Buffers In this technique, the buffers are located at the OC of the switch element. The assumption is that many cells from the IC can cross the internal interconnection network and arrive to the outlets. This solution requires use of a very fast internal pass. In order to allow a non-blocking switch, the interconnection network and the output buffer have to be capable of handling N cells at one cell time (when N in the number of ICs).
When output buffers are in use, no arbitration has to be used. The control of the output is based on a simple FIFO logic.
Output Buffers.
Central Queueing In the central queueing approach, the queueing buffers are not dedicated to a single inlet (as in the input buffer approach) or to a single outlet (as in the output buffer approach), but shared between all inlets and outlets. Each coming cell will be directly stored in the central storing element. Every outlet will identify the cells destined to it in a FIFO discipline.
From the queueing point of view, this method is the most efficient and required the smallest total storage to allow minimal cell loss in heavy load conditions. Since the available memory on an integrated circuit switching element is limited, it is possible to achieve low cell-loss probabilities when using the central queueing approach.
The disadvantages of this approach are that very fast memory elements are required to allow all the coming cells and outgoing cells access to the memory ports at the same time, and big complexity in the queue management.
Technical Aspects The realization of the three queueing approaches are very different. The differences are in three main aspects:
Example- Knockout Switching Element The following paragraphs describe the general structure of the Knockout switching element. The Knockout switch was first introduced by Yeh in 1987. The Knockout switch can grow to a large size by composing small entities, to create bigger switching element or as a switching fabric.
The Knockout switch is based on a the output buffering (queueing) approach. As mentioned before one of the disadvantages of the output queueing methods is the fast memory access required to achieve a small cell loss rate. The Knockout is trying to overcome this disadvantage.
The Knockout switch has N inlets and N outlets. The interconnection network is a matrix type. N broadcast buses, one of each inlet, connects to each of the inlets. Each outlet is connected to all inlets via a bus interface of N inputs, connected to each individual broadcast bus. This means that the interconnection network is non-blocking, and at the input of the bus interface there is no cell loss.
Knockout Switching Element
The bus structure has the major advantage that each bus is driven by only one inlet. This structure allows simple implementation and high bandwidths on the interconnection network.
At a bus interface, several cells may arrive simultaneously. All can (in the worst case) be destined to a single output. Therefore, the bus interface requires some kind of queueing. Since N cells can be destined to a bus interface at one cell time, the bus interface has to use very fast memory elements to guarantee zero cell loss. In order to simplify the implementation and reduce the required memory operation speed, a non-zero loss method is implemented. The is switch realized as an intelligent bus interface , which acts as a concentrator , with a non-zero cell loss probability.
At the top of the bus interface N filters are located, each one of them connected to one of the N inlet broadcast buses. The cell filters examine the address of the incoming cells. If the cell is destined to the outlet related to the bus interface the cell is passed to the concentrator .
The next part after the bus interface is the concentrator , which concentrates N inputs to L outputs (where L<= N). If in the same cell time, k cells are destined to the same outlet and k>L , a (L-k) cells will be lost in the concentrator . The concentrator itself is built of very simple building blocks. Those biulding blocks are basically a switch in which 2 inputs contend for a winner output. If only one cell is present at the input at a time, it will be selected as a winner output. If two cells are present at a time in the inputs, one cell is selected as a winner and the second one, the loser, it transferred to contend on the next stage.
The probability of losing a cell in the concentrator must not be larger than the probability of losing cells elsewhere in the switch element. Statistical calculations show that if L=12, a cell loss probability of 10^(-10) can be achieved for any load and any value of N.
The next stage in the Knockout switch is the output buffers . L dual port buffers are connected to the L concentrator outputs. In order to distribute the load on the output FIFOs (and reducing the total amount of memory required for each bus interface) a sifter stage is provide. The shifter guarantee that all L buffers are equally (uniformly) loaded and optimally used.
More information About Switching More information can be found on the following switching elements:
Signing off
Shashwat Pandey