BRIEF PROCESSOR FEATURE DESCRIPTION
(3 December 1986)
INTEL 8088
PC/HT AND IBM PC XT PROCESSOR CHIP
MAXIMUM CLOCK SPEED OF 8 MHz
MAXIMUM PHYSICAL MEMORY OF 1 MegaBytes
INTERNAL DATA BUS SIZE OF 16 BITS
EXTERNAL DATA BUS SIZE OF 8 BITS
MAXIMUM BUS BAND WIDTH OF 2 MegaBytes/Sec
TWENTY FOUR REGISTERS
INTEL 8086 INSTRUCTION SET
INTEL 8086
B21 AND B22 PROCESSOR CHIP
MAXIMUM CLOCK SPEED OF 10 MHz
MAXIMUM PHYSICAL MEMORY OF 1 MegaBytes
INTERNAL DATA BUS SIZE OF 16 BITS
EXTERNAL DATA BUS SIZE OF 16 BITS
MAXIMUM BUS BAND WIDTH OF 5 MegaBytes/Sec
TWENTY FOUR REGISTERS
INTEL 80186
B26 AND B27 PROCESSOR CHIP
MAXIMUM CLOCK SPEED OF 8 MHz
MAXIMUM PHYSICAL MEMORY OF 1 MegaBytes
MAXIMUM SEGMENT SIZE OF 64 KiloBytes
INTERNAL DATA BUS SIZE OF 16 BITS
EXTERNAL DATA BUS SIZE OF 16 BITS
MAXIMUM BUS BAND WIDTH OF 6.25 MegaBytes/Sec
TWENTY FOUR REGISTERS
SUPER-SET OF INTEL 8086 INSTRUCTION SET
RATED TWICE THE PERFORMANCE OF INTEL 8086
INTEL 80286
B28, PC/microIT, PC/IT AND IBM AT PROCESSOR CHIP
MAXIMUM CLOCK SPEED OF 12.5 MHz
MAXIMUM PHYSICAL MEMORY OF 16 MegaBytes
MAXIMUM LOGICAL MEMORY OF 1 GigaBytes
MAXIMUM SEGMENT SIZE OF 64 KiloBytes
INTERNAL DATA BUS SIZE OF 16 BITS
EXTERNAL DATA BUS SIZE OF 16 BITS
MAXIMUM BUS BAND WIDTH OF 12.5 MegaBytes/Sec
TWENTY FOUR REGISTERS
FOUR STAGE PIPELINE ARCHITECTURE
TWO MODES OF OPERATION:
REAL MODE
PHYSICAL MEMORY ADDRESS LIMITED TO 1 MegaByte
INTEL 8086 / 8088 EMULATION
PROTECTED VIRTUAL ADDRESS MODE
VIRTUAL MEMORY SEGMENTS
PROTECTION ARCHITECTURE
SUPPORT OF BINARY CODED DECIMAL (BCD) DATA TYPES
SUPER-SET OF INTEL 80186 INSTRUCTION SET
APPROXIMATELY TWICE AS FAST AS INTEL 80186
INTEL 80386
B38 AND BXX PROCESSOR CHIP
MAXIMUM CLOCK SPEED OF 16 MHz
MAXIMUM PHYSICAL MEMORY OF 4 GigaBytes
MAXIMUM LOGICAL MEMORY OF 64 TeraBytes (246)
MAXIMUM SEGMENT SIZE OF 4 GigaBytes
INTERNAL AND EXTERNAL DATA BUS SIZE OF 32 BITS
MAXIMUM BUS BAND WIDTH OF 32 MegaBytes/Sec
THIRTY REGISTERS
SPECIAL HIGH-SPEED (3.5-16 mSec) TASK SWITCHING HARDWARE
ADDITION OF TWO 32 BIT REGISTERS IN 2 CLOCK CYCLES
MULTIPLICATION OF TWO 32 BIT REGISTERS IN 9 TO 42 CLOCKS
SIX STAGE PIPELINE ARCHITECTURE
SUPER-SET OF INTEL 80286 INSTRUCTION SET
REAL AND PROTECTED VIRTUAL ADDRESS MODES
VIRTUAL MEMORY PAGING AND SEGMENTATION
VIRTUAL INTEL 8086 MODE ( REAL MODE )
SUPPORT OF BIT STRING DATA TYPE FOR GRAPHICS
SPECIAL SUPPORT FOR OFF-CHIP CODE AND DATA CACHE
SEGMENT DESCRIPTORS DEFINING PROTECTION, TYPE AND LIMITS
FOUR LEVEL HIERARCHAL MEMORY PROTECTION SCHEME
EXTENDED DEBUGGING CAPABILITIES
APPROXIMATELY TWICE AS FAST AS INTEL 80286
RELATIVE B20 PROCESSOR PERFORMANCE
PERFORMANCE OF PROCESSORS IN WORKSTATIONS
WORKSTATION PROCESSOR CLOCK SPEED THROUGHPUT
B21 (TURBO) 8086 8 MHz .75 MIPS
B22 8086 3.3 MHz .25 MIPS
B26 80186 8 MHz 1 MIPS
B27 80186 8 MHz 1 MIPS
B28 80286 8 MHz 1.5 - 2 MIPS
B38 80386 16 MHz (EST.) 3-4 MIPS
(* ALL PROCESSOR PERFORMANCE FIGURES ARE ESTIMATES AND ARE NOT EMPIRICALLY DERIVED *)