By Jamil Khatib

By Jamil Khatib

Copyright 2002

Introduction to Programmable logic devices

The main aim of this article is to give a small introduction to electronics design through describing programmable logic design techniques. It is useful for new electronics engineers and hobbies who like to build there own circuits and designs in easy and modern way. This article requires the basic knowledge of electronics and digital design.

(Introduction to digital design may come in the future)

Electronics design

The invention of the transistor has changed not only the electronics industry but the whole world because of its size speed and design simplicity. Transistor circuits are used in many circuits starting from amplifiers up to musical instruments circuits.

The transistors are used as switches to turn circuits on and off. This phenomenon helped in the design of many circuits such as alarms, control circuits and all circuits that are based on on-off technique.

Digital design makes use of this on-off that is symbolized by 1-0. These 0s and 1s are the basics of the Boolean arithmetic.

Digital design

Digital design makes use of the Boolean functions to implement its circuits. AND, OR, NOT are the basic functions that can generate all other functions. All Arithmetic and logic functions can be implemented using these functions.

2-bit half adder example:
Sum = (x AND NOT y) OR (NOT x AND y)

Carry =(x AND y)

Besides that, Flip-flops and registers are used in digital design to implement memory or storage element in the design, so the circuit can remember its old state to calculate the new state and act accordingly.

There are two types of digital circuits synchronous (Clocked) and asynchronous (non-clocked) circuits.

Advantages of digital design:

Simplicity: It is easier to design and build complex digital circuit rather than analogue one. See examples section.
Debug: Since digital circuits are based on on-off technique, it is easier to debug the circuits because each out put should be either in the 0 state or in the 1 state.

Digital Logic devices

Transistors are the basic components for all other devices. They are used in very simple circuits as on-off switches.
Primitive Digital devices & LSIs (Large Scale Integration). Old digital designs used primitive components such as AND, OR, NOT, XOR and flip-flops. These components are encapsulated in small chips (IC). LSIs are chips that encapsulate complex functions such as decoders, multiplexers, adders and arithmetic units.
VLSIs (Very Large Scale Integration) are complex chips that integrate several functions and components such as processors, CPUs, controllers, communication protocols, memories and more.
Programmable logic devices (PLD) are integrated circuits with internal logic gates that are connected together through fuses. The functionality of the chip is defined by a process that is called programming. The programming the chip is simply blowing some fuses between some of the on chip resources (gates). This operation disconnects the path between the resources and keeps some connections between others. ROMs (Read Only Memories), PALs (Programmable array logic) and PLAs (Programmable Logic Arrays) are examples of PLDs. The main difference between these devices is the position of the fuses and the fixed connection between gates. Note: since the on-chip resources are connected through fuses, the programming process can be done once.

The figure below shows the structure of a PAL device. It is composed of AND and OR gates connected together via fuse array.

Structure of PAL

ASICs (Application Specific Integrated Circuits) are another type of electronics devices. These chips are custom chips built for specific needs. There are two main kinds of ASICs, sea of gates and cell-based chips. Sea of gates chips are made of on chip gates and wires. The connections between the gates are defined during the fabrication of the chip. The custom chips are fully custom and all chip resources are defined during the fabrication of the chip.
CPLDs Complex Programmable Logic Devices: a more Complex PLD that consists of an arrangement of multiple PLD-like blocks on a single chip. It is more like complex PALs described earlier but with more resources.

FPGAs Field Programmable Gate Arrays are devices featuring a general structure that allows very high logic capacity. Whereas CPLDs feature logic resources with a wide number of inputs (AND planes), FPGAs offer more narrow logic resources. FPGAs also offer a higher ratio of flip-flops to logic resources than do CPLDs.

Generic FPGA architecture

FPGA resources and architecture

FPGAs are mainly characterized by their logic size and resources and their speed.

Logic cells: All FPGAs are based on the replication of small circuit blocks in an array. User circuits are decomposed into smaller circuits and mapped in several logic cells. Logic cells usually composed of Flip-flop and some logic gates this depends on the FPGA vendor and family. Note:Each FPGA vendor has its own name for Logic Cell and how it is structured. Logic block & Logic Element are examples of such names.
LUTs: Look-Up Tables are more like ROMs. Most combinational logic and product terms are implement in them. Usually LUTs exists in Logic cells.
Memory resources: Some FPGA families encapsulate some memory resources such as SRAM, dual port memory and CAM. They are usually used in special way of HDL coding or using specific components in the schematic entry.
Routing resources. These are composed usually by routing channels, wires, and switches that can connect between on chip FPGA resource such as logic cells, memory resource and so on.
Pins: FPGAs can have different configuration for IO pins. Some pins can be configured as TTL, CMOS, PCI, AGP and more. So FPGAs can be used to convert between different circuit technologies.
Clock pins and PLLs: Some FPGAs have dedicated fast pins for clocks, Resets or any fast logic. Some FPGAs may have PLLs and clock management blocks such as clock multipliers and dividers.

FPGA Components

Xilinx Spartan and Virtex families
Altera Apex and Acex families
Actel
Lucent Orca devices

Xilinx's Virtex Slice

Altera's Apex Logic Element

FPGA boards

There are many FPGA demo and application boards. These boards range from small FPGA with some external headers and connectors to very large and complex boards with lot of interfaces chips and even FPGAs.

Here are some resources where you can find some boards

Xess boards (some of them are suitable for beginners)
Altera SOPC boards
http://www.burched.com.au/B5Spartan2.html

Design flow techniques

FPGA design flow is the same for professional engineers, students and hobbies; the only difference is the complexity of the design and tools with extra optimization options.

- Specification or definition: Defining the problem and what need in an important step before the design.

Design Entry: this step is what we usually do with pencil and paper but in a computer organized way and it is the most important step since it describes the design. There are two ways for design entry

Schematics drawing which is the same as drawing the schematics of the board or circuits. The Components are placed on sheets and connected together. This method is not useful for very large designs which need lot of components.
HDL is a technique to describe the electronics (specially the digital) circuits using software like programming. The HDL is simply like the software C/C++, Pascal or Basic code. For more information about this refer to the HDL technique section later on.

Simulation: Although FPGAs can be easily erased and reprogrammed if any error occurred, but large designs it is better to make pre-debug for the system before programming it. This way will save extra time and reduces number of times needed for programming the FPGA.
Synthesis is the process of converting and detecting circuits from the HDL code. This step is not used when schematic entry is used.
Place and route: this step is used to map and place all design components (after synthesis for HDL code or simplification for schematics) into FPGA resources (to be described later on). After placing and mapping the design components it connects them together as defined by the design using the on-chip routing channels and wires. This step also maps the design pins into the FPGA pins.
Bit stream generation. The bit stream (or the programming file) holds all information about the design and how it is mapped into the FPGA resources and how all FPGA internal switches must act.
Programming the bit stream file is dependent on the device and the vendor, each one has its specific programming method and it is usually aided by the FPGA vendor software.

The last 3 steps are usually done by FPGA vendor specific tools.

HDL technique

Hardware Description Languages (HDL)

As described earlier HDL is one of the design entry methods for FPGA design. In fact it could be a generic method for hardware design. It is simply a way of hardware design description in a human like language, which looks like software programming.

There are several HDL languages some are so simple and some are complex. Most languages can describe digital hardware using the basic digital operators such as AND, OR etc. Other languages are more complex and advanced so that it allows the user to describe the design in more human readable logic. For example it allows the user to use if, case and loops statements which make him focus on the design itself not on the hardware. Most HDL languages define IO pins of the design and its internal functionality. VHDL, Verilog and AHLD are examples of HDLs.

For examples about the VHDL check the design examples section later on.

Tools

Simulation: Modelsim, Active-HDL, NC-SIM

Synthesis: Leonardo, Synplify, Synopsys

Place and Route: Altera Quartus, Xilinx Foundation.

Examples of Free tools

Most of FPGA vendors provide free light version of simulation, synthesis and place and route tools that are useful for small and mid size designs. These tools are suitable for hobbies and students and even companies that do not need lot of features.

Design Examples in VHDL

Half adder

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

ENTITY Adder_ent IS

PORT (

Op1 : IN std_logic; -- Operand 1

op2 : IN std_logic; -- Operand 2

carry : OUT std_logic; -- Output carry

Result : OUT std_logic); -- Result

END Adder_ent;

ARCHITECTURE behavior OF Adder_ent IS

BEGIN -- behavior

Result <= (Op1 AND NOT Op2) OR (NOT Op1 AND Op2);

Carry <= Op1 AND Op2;

END behavior;

8 bit Adder

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

USE ieee.std_logic_unsigned.ALL;

ENTITY Adder_ent IS

PORT (

clk : IN std_logic; -- System clock

rst_n : IN std_logic; -- System reset

Op1 : IN std_logic_vector(7 DOWNTO 0); -- Operand 1

op2 : IN std_logic_vector(7 DOWNTO 0); -- Operand 2

Result : OUT std_logic_vector(7 DOWNTO 0)); -- Result

END Adder_ent;

ARCHITECTURE behavior OF Adder_ent IS

BEGIN -- behavior

PROCESS (clk, rst_n)

BEGIN -- PROCESS

IF rst_n = '0' THEN -- asynchronous reset (active low)

Result <= (OTHERS => '0');

ELSIF clk'event AND clk = '1' THEN -- rising clock edge

Result <= Op1 + op2;

END IF;

END PROCESS;

END behavior;

Counter

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

USE ieee.std_logic_unsigned.ALL;

ENTITY Adder_ent IS

PORT (

clk : IN std_logic; -- System clock

rst_n : IN std_logic; -- System reset

Count : OUT std_logic_vector(7 DOWNTO 0)); -- Count

END Adder_ent;

ARCHITECTURE behavior OF Adder_ent IS

SIGNAL counter : std_logic_vector(7 DOWNTO 0); -- internal counter

BEGIN -- behavior

PROCESS (clk, rst_n)

BEGIN -- PROCESS

IF rst_n = '0' THEN -- asynchronous reset (active low)

Counter <= (OTHERS => '0');

ELSIF clk'event AND clk = '1' THEN -- rising clock edge

Counter <= counter + 1;

END IF;

END PROCESS;

count <= counter;

END behavior;

7-Segment decoder

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

ENTITY Decoder IS

PORT (

InBin : IN std_logic_vector (3 DOWNTO 0);

Display : OUT std_logic_vector (6 DOWNTO 0));

END Decoder;

ARCHITECTURE rtl OF decoder IS

SIGNAL t : std_logic_vector (6 DOWNTO 0);

BEGIN

seg_process : PROCESS (InBin)

BEGIN

CASE InBin IS

WHEN "0000" => t <= "1111110";

WHEN "0001" => t <= "0110000";

WHEN "0010" => t <= "1101101";

WHEN "0011" => t <= "1111001";

WHEN "0100" => t <= "0110011";

WHEN "0101" => t <= "1011011";

WHEN "0110" => t <= "0011111";

WHEN "0111" => t <= "1110000";

WHEN "1000" => t <= "1111111";

WHEN "1001" => t <= "1110011";

WHEN "1010" => t <= "1110111";

WHEN "1011" => t <= "0011111";

WHEN "1100" => t <= "1001110";

WHEN "1101" => t <= "0111101";

WHEN "1110" => t <= "1001111";

WHEN OTHERS => t <= "1000111";

END CASE;

Display <= NOT t;

END PROCESS seg_process;

END rtl;

Why programmable logic

There is No need for complex fabrication process to implement designs using FPGAs. If the board exists with the FPGA component on it, only the bit stream file is needed to program the FPGA and change its functionality.
It is easier to design, debug and modify FPGAs rather than ASICs.

Building Custom CPUs

Since the FPGAs can be easily programmed and designed, companies can build and implement their own custom CPUs. For that reason there are many Free CPUs on the web like: OpenRISC from opencores.org .

Run time reconfigurable logic

One of the advantages of configurable logic that can it can be reprogrammed dynamically on run time. This means that the FPGA configuration can be changed during operation. The advantage of this feature that one can put in an FPGA several designs. These designs are not operating on the FPGA at the same time, they are loaded only when they are needed. In this case we can put designs in a single FPGA much more than its actual physical size. For example there are some designs need to run only at the beginning of the system, after that they are not used (such as initialization). Other designs can operate only when the user requests them. So if we put all these designs together on the FPGA we will need large FPGA, but if we load and unload them as needed we can reduce the FPGA size we need.

Open Source Hardware

As in the world of open source free software, hardware designs can also be open source and free through the use of the FPGAs and HDLs. Designers and hobbies can write HDL code simulate it and then program it to the FPGA board. The HDL code can be shared between designers all over the world and they can review and edit it by their own. In short HDL code and FPGA board are like software code and computers for open source software. As there is a free open source Linux operating system, one day we will have free open source CPUs and computers.

References

Digital design by Morris Mano.
Field Programmable Gates Array by Oldfield and Dorf.
http://klabs.org/richcontent/Tutorial/fpga/Toronto_tutorial.pdf Architecture of FPGAs and CPLDs: A Tutorial (The best document)
http://klabs.org/richcontent/Tutorial/PLD_Definitions.htm
http://hobbes.inesc.pt/~hcn/cid/xprojecto2.pdf
www.optimagic.com
www.xilinx.com
www.altera.com
www.xess.com
http://www.eecg.toronto.edu/~lewis/ece451/vhdl_examples.html
http://www.mcmanis.com/chuck/robotics/fpga/

Request for help

I am looking for someone to do technical Arabic translation of this document
Please send me your comments or any extra information that may be added to this document to jamilkhatib75@yahoo.com