Next: Bibliography
Up: RTR applications
Previous: Reconfigurable logic limitations
Extra features must be added to the FPGAs to increase their usability, such as:
- On-chip memory must be increased.7
- Special-purpose blocks such as Arithmetic units [14] are needed to increase FPGA usability in the arithmetic computation instead of converting these operations to bit operations that consumes look-up tables ``LUT''.
- Memory and micro-processors interfacing support must be included in the FPGA chips to reduce the overhead needed to interface to these devices8 [11]. Xilinx XC6200 FPGA family has parallel programming facility where each internal cell can be seen by the microprocessor as if it is a memory cell.
- Enhanced partial reconfigurable FPGA must be built to reduce the configuration time. Xilinx XC6200 family supports the partial reconfiguration with reconfiguration bandwidth 33.3 MB/sec, but this family is optimized for configuration speed and not logic density. Both Atmel and national semiconductors have their own partial reconfigurable FPGA families.
To conclude, reconfigurable logic will become more considerable for real world applications after high speed configuration FPGA architectures are developed with intelligent software that ease both the system use and design.
Jamil Khatib
1998-10-16