/*
-------------------------------------------------------------------------------
-- Title      :  Barrel Shifter
-- Project    : Arithmetic cores
-------------------------------------------------------------------------------
-- File        : BarrelShifter.v
-- Author      : Jamil Khatib  (khatib@ieee.org)
-- Organization: OpenCores Project
-- Created     : 2000/09/23
-- Last update : 2000/09/23
-- Platform    : 
-- Simulators  : Modelsim 5.3XE/Windows98
-- Synthesizers: 
-- Target      : 
-- Dependency  : 
-------------------------------------------------------------------------------
-- Description: 
-------------------------------------------------------------------------------
-- Copyright (c) 2000 Jamil Khatib
-- 
-- This Verilog code file is an open design; you can redistribute it and/or
-- modify it and/or implement it after contacting the author
-- You can check the draft license at
-- http://www.opencores.org/OIPC/license.shtml

-------------------------------------------------------------------------------
-- Revisions  :
-- Revision Number :   1
-- Version         :   0.1
-- Date            :   23 Sep 2000
-- Modifier        :   Jamil Khatib (khatib@ieee.org)
-- Desccription    :   Created
-- ToDo			   :   Define Shift Direction and write RTL code

-------------------------------------------------------------------------------
*/



module BarrelShifter(inReg,outReg,ShSize);

parameter REGSIZE = 16;
parameter SHIFTSIZE = 5;

input [REGSIZE-1:0] inReg;
input [SHIFTSIZE -1:0] ShSize;
output [REGSIZE-1:0] outReg;
  
assign outReg = inReg >>ShSize;

endmodule