-------------------------------------------------------------------------------
-- Title      :  Cores Package
-- Project    :  Utility library
-------------------------------------------------------------------------------
-- File        : tools.vhd
-- Author      : Jamil Khatib  (khatib@ieee.org)
-- Organization: OpenIPCore Project
-- Created     : 2000/11/03
-- Last update : 2000/11/03
-- Platform    : 
-- Simulators  : Modelsim 5.3XE/Windows98
-- Synthesizers: 
-- Target      : 
-- Dependency  : ieee.std_logic_1164
--             : utility.tools_pkg
-------------------------------------------------------------------------------
-- Description:  This package contains set of usefull functions and procedures
-------------------------------------------------------------------------------
-- Copyright (c) 2000 Jamil Khatib
-- 
-- This VHDL design file is an open design; you can redistribute it and/or
-- modify it and/or implement it after contacting the author
-- You can check the draft license at
-- http://www.opencores.org/OIPC/license.shtml

-------------------------------------------------------------------------------
-- Revisions  :
-- Revision Number :   1
-- Version         :   0.1
-- Date            :   3rd Nov 2000
-- Modifier        :   Jamil Khatib (khatib@ieee.org)
-- Desccription    :   Created
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;

library Utility;
use Utility.tools_pkg.all;

package cores_pkg is
-------------------------------------------------------------------------------
-- Components definition
-------------------------------------------------------------------------------
  component BarrelShifter
    generic (
      REGSIZE   :     integer;          -- Register Size
      DIRECTION :     integer);         -- Shift Direction
    port (
      inReg     : in  std_logic_vector(REGSIZE -1 downto 0);  -- Input Register
      ShSize    : in  std_logic_vector(log2(REGSIZE) -1 downto 0);  -- Shift Size
      outReg    : out std_logic_vector(REGSIZE -1 downto 0));  -- Shifted Result
  end component;

-------------------------------------------------------------------------------
end cores_pkg;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
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