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Using Text Files In Simulation

I had intended to write a few notes on the use of files as stimulus input and results logging during VHDL simulation, but I found a site by Stefan Doll of Intrinsix which more than covers all of this topic. His explanation of design verification is an absolute must.

His VHDL text formatting package (txt_util.vhd) is extremely useful, but I have made a slight modification. I have introduced a new procedure, printt. This is exactly the same as the print procedure written by Doll, except that it appends the current simulation time to the printed string. The file is available for download.

Easics have also produced a text formatting package which can be downloaded for free.