Experience Summary

Ø       Working as an ASIC Design Engineer  in Bisquare Technologies P Ltd, New Delhi  since October 2000.

Ø       From January 2000 to September 2000 working as Design Engineer in Accell Technologies Ltd ., Chennai

Technical Knowledge

Ø       Thorough knowledge in Verilog

Ø       Knowledge in VHDL

Ø       Exposure to ASIC Methodologies

Ø       Design Assignments Implementation in Xilinx FPGA

Ø       Good Digital Design knowledge

Ø       Exposure to Project Management

Tools Handled

Ø       ModelTech simulation tool for VHDL&Verilog

Ø       Leonardo Spectrum Synthesizer

Ø       Xilinx Synthesizer (FPGAs)

Technologies Worked

Ø       IEEE 1394 (FIREWIRE)

Ø       Open Core Protocol(OCP)

Ø       ARM 7 Processor

Ø       AMBA Bus - AHP

Education

Ø       Post Graduate Diploma in VLSI Design From Accel Technologies Ltd.,Chennai. Completed on July 2000 with 89%

Ø       Bachelor of Engineering in Electronics and communication Engineering From Bharathidasan University,Thiruchiraapalli.

            At AAM Engineering College,Thanjavur. With First Class -70%,Completed on 1999 May.

 Project Handled

    IEEE 1394-Link layer

(Bus functional model):

Language: Verilog HDL

Team Size: 3 Engineers

Duration: 4 weeks

Role: Design

Implementation Tool: Xilinx Synthesizer (FPGAs)

Time: 2000 April 18th to July 18th

Company: Accel Technologies Ltd., Chennai

 Description : IEEE - 1394 is a serial bus used for high-speed data

transfer. The data transfer is handled by layered protocol involving 3 layers- transaction, link and physical. The link layer packetizes the data into IEEE 1394 format and links that to the physical layer.

Open Core protocol

Language : Verilog HDL

Team Size:3 Engineers

Roll: Design ,coding and verification.

Company: Bisquare Technologies P Ltd., New Delhi.

Client : Sonics Inc.,USA.

Description:

         Open core protocol is an on chip protocol developed by Sonics incorporated , USA. . This connects the cores of system on chip effectively and guarantees the reusability of the cores. In our project our team is making the cores given by sonics as an OCP compliant core by designing a bridge interface for that core.

The cores wrapped

    1.AMBA BUS – AHB Master

    2.ARM7  - Master bridge        And continuing with some other cores