suman

SUMAN GOUD, JANAGAMA

2711, West Central Ave, Apt # D-12, Toledo, OH- 43606, Phone: 419-475-7622

A Capable, Highly motivated, Honest, Hardworking and Co-operative Electrical Engineer.

OBJECTIVE:

     To obtain a challenging position in the field of Digital VLSI/ ASIC Design/ VHDL Modeling.

SKILLS:

     Proficient in Digital Design, Circuit Design, VLSI Design philosophies.

     Conversant with VLSI EDA tools (VHDL, PSpice, Galileo, Leonardo, Xilinx FPGA tools).

EDUCATION:

   M.S in Electrical Engineering (VLSI)

August 2000 – Present The University of Toledo, Toledo, OH. GPA: 3.769

B.E in Electrical and Electronics Engineering

August 1996- June 2000 C.B.I.T, Hyderabad, A.P, India. GPA: 3.75

PROJECTS:

CMOS CIRCUIT DESIGN

(Till date)

     Design of PAD Driver: A PAD driver in 0.4 micron technology was designed with minimum delay by adjusting the capacitance to current ratio
     at each transistor. The design was simulated in PSpice.

VHDL

     1. Positional Location of a Wireless Interface Unit: Algorithm for positional location for cellular users from IEEE paper "Simple Solutions for
        Hyperbolic and related position fixes" was successfully implemented. 
        This model was simulated using MATLAB.

     2. IEEE 1149.1: Literature study of IEEE 1149.1 and implementation of IEEE 1149.1 Device Architecture in VHDL.

     3. Error Correction Technique: Literature study and simulation of Bit Stuffing Error Correction method using VHDL.

DIGITAL VLSI

(Till Date)

      1. Design of Shift Register: A four-bit wide four bit long bi-directional dynamic shift register with two-phase clocking scheme.
          The Mentor Graphics EDA tools Led and Lsim were used for layout and simulation.

      2. Design of 6-Transistor memory cell: Design and layout of 6-transistor memory cell occupying minimum area in AMI 1.5
          technology was done using the Mentor Graphics tool Led.

MASTER’S PROJECT

          Study of GSM and Simulation of algorithm for Positional Location of Cellular Phones: 
             History and developments in GSM, Cell Structure and reuse distance, SAT and DCC, TDMA, FDMA,  Frequency allocation techniques,
             Controlling and Signaling procedures with GSM, Multipath propagation problem, Timing Structure and Concept of frames in GSM,
             TACS and AMPS.Algorithm for positional location of a cellular was derived from IEEE paper and implemented in VHDL.
             Structural description was used at the top level and behavioral description was used for components.

RELAVENT COURSES:

Digital Design using VHDL
Digital VLSI Design I
Digital VLSI Design II
Advanced Computer Architecture
Digital CMOS VLSI Design
FPGA
Digital Signal Processing

COMPUTER SKILLS

Languages: VHDL, C, HTML and Assembly (8085).

Platforms: UNIX, Windows NT/ 00 and DOS.

EDA Tools: PSpice, VHDL, Mentor Graphics Tools- Design Architect, Layout Editor, Leonardo, Galileo and XILINX FPGA tools.

*References available on request.

*Willing to relocate.