This file is from the book:
Microprocessor Technology ISBN 0835943925
Scan done by:
Alvin Albrecht aralbrec@concentric.net
OCR , retyping, and checking done by:
Vaggelis Kapartzianis zx32@usa.net
Thanks to you guys for this great work :-)
LEGEND
======
IO - internal CPU Operation
MR - Memory Read ODL - Operand Data Read of Low Byte
MRH - Memory Read of High Byte PR - Port Read
MRL - Memory Read of Low Byte PW - Port Write
MW - Memory Write SRH - Stack Read of High Byte
MWH - Memory Write of High Byte SRL - Stack Read of Low Byte
MWL - Memory Write of Low Byte SWH - Stack Write of High Byte
OCF - Op Code Fetch SWL - Stack Write of Low byte
ODH - Operand Data Read of High Byte ( ) - Number of T-States in that Machine Cycle
Z80 INSTRUCTION BREAKDOWN BY MACHINE CODE
=========================================
MACHINE CYCLE
INSTRUCTION BYTES M1 M2 M3 M4 M5
TYPE
====================================================================================================
LD r,s 1 OCF(4)
LD r,n 2 OCF(4) OD(3)
LD r,(HL) 1 OCF(4) MR(3)
LD (HL),r OCF(4) MW(3)
LD r,(IX+d) 3 OCF(4)/OCF(4) OD(3) IO(5) MR(3)
LD (IX+d),r OCF(4)/OCF(4) OD(3) IO(5) MW(3)
LD (HL),n 2 OCF(4) OD(3) MW(3)
BC
LD A,(DE) 1 OCF(4) MR(3)
BC
LD (DE),A OCF(4) MW(3)
LD A,(nn) 3 OCF(4) ODL(3) ODH(3) MR(3)
LD (nn),A OCF(4) ODL(3) ODH(3) MW(3)
I
LD A,R 2 OCF(4)/OCF(5)
I
LD R, A
LD dd,nn 3 OCF(4) ODL(3) ODH(3)
LD IX,nn 4 OCF(4)/OCF(4) ODL(3) ODH(3)
LD HL,(nn) 3 OCF(4) ODL(3) ODH(3) MRL(3) MRH(3)
LD (nn),HL OCF(4) 0DL(3) ODH(3) MWL(3) MWH(3)
LD dd,(nn) 4 OCF(4)/OCF(4) ODL(3) ODH(3) MRL(3) MRH(3)
LD (nn),dd OCF(4)/OCF(4) ODL(3) ODH(3) MWL(3) MWH(3)
LD IX,(nn) OCF(4)/OCF(4) ODL(3) ODH(3) MRL(3) MRH(3)
LD (nn),IX OCF(4)/OCF(4) 0DL(3) ODH(3) MWL(3) MWH(3)
LD SP,HL 1 OCF(6)
LD SP,IX 2 OCF(4)/OCF(6)
PUSH qq 1 0CF(5) SWH(3) SWL(3)
SP-1 ---> SP-1 --->
PUSH IX 2 OCF(4)/0CF(5) SWH(3) SWL(3)
SP-1 ---> SP-1 --->
POP qq 1 OCF(4) SRH(3) SRL(3)
SP+1 ---> SP+1 --->
POP IX 2 OCF(4)/0CF(4) SRH(3) SRL(3)
SP+1 ---> SP+1 --->
EX DE,HL 1 OCF(4)
EX AF,AF' 1 OCF(4)
EXX 1 OCF(4)
EX (SP),HL 1 OCF(4) SRL(3) SRH(4) SWH(3) SWL(5)
SP+1 ---> SP-1 --->
EX (SP),IX 2 OCF(4)/OCF(4) SRL(3) SRH(4) SWH(3) SWL(5)
SP+1 ---> SP-1 --->
LDI 2 OCF(4)/OCF(4) MR(3) MW(5)
LDD
CPI
CPD
LDIR 2 OCF(4)/OCF(4) MR(3) MW(5) IO(5)*
LDDR
CPIR *only if BC<>O
CPDR
ALU A,r 1 OCF(4)
ADD ADC
SUB SBC
AND OR
XOR CP
ALU A,n 2 OCF(4) OD(3)
ALU A,(HL) 1 OCF(4) MR(3)
ALU A,(IX+d) 3 OCF(4)/OCF(4) OD(3) IO(5) MR(3)
DEC
INC r 1 OCF(4)
DEC
INC (HL) 1 OCF(4) MR(4) MW(3)
DEC
INC (IX+D) 2 OCF(4)/OCF(4) OD(3) IO(5) MR(4) MW(3)
DAA 1 OCF(4)
CPL
CCF
SCF
NOP
HALT
DI
EI
NEG 2 OCF(4)/OCF(4)
IM0
IM1
IM2
ADD HL,ss 1 OCF(4) IO(4) IO(3)
ADC HL,ss 2 OCF(4)/OCF(4) IO(4) IO(3)
SBC HL,ss
ADD IX,pp
INC ss 1 OCF(6)
DEC ss
DEC IX 2 OCF(4)/OCF(6)
INC IX
RLCA 1 OCF(4)
RLA
RRCA
RRA
RLC r 2 OCF(4)/OCF(4)
RL
RRC
RR
SLA
SRA
SRL
RLC (HL) 2 OCF(4)/OCF(4) MR(4) MW(3)
RL
RRC
RR
SLA
SRA
SRL
RLC (IX+d) 4 OCF(4)/OCF(4) OD(3) IO(5) MR(4) MW(3)
RL
RRC
RR
SLA
SRA
SRL
RLD 2 OCF(4)/OCF(4) MR(3) IO(4) MW(3)
RRD
BIT b,r 2 OCF(4)/OCF(4)
SET
RES
BIT b,(HL) 2 OCF(4)/OCF(4) MR(4)
SET b,(HL) 2 OCF(4)/OCF(4) MR(4) MW(3)
RES
BIT b,(IX+d) 4 OCF(4)/OCF(4) OD(3) IO(5) MR(4)
SET b,(IX+d) 4 OCF(4)/OCF(4) OD(3) IO(5) MR(4) MW(3)
RES
JP nn 3 OCF(4) ODL(3) ODH(3)
JP cc, nn
JR e 2 OCF(4) OD(3) IO(5)
JR C,e 2 OCF(4) OD(3) IO(5)*
JR NC,e *If condition is met
JR Z,e
JR NZ,e
JP (HL) 1 OCF(4)
JP (IX) 2 OCF(4)/OCF(4)
DJNZ,e 2 OCF(5) OD(3) IO(5)*
* If B<>0
CALL nn 3 OCF(4) ODL(3) ODH(4) SWH(3) SWL(3)
CALL cc,nn SP-1 ---> SP-1 --->
cc true
CALL cc,nn 3 OCF(4) ODL(3) ODH(3)
cc false
RET 1 OCF(4) SRL(3) SRH(3)
SP+1 ---> SP+1 --->
RET cc 1 OCF(5) SRL(3)* SRH(3)*
* If cc is true
SP+1 ---> SP+1 --->
RETI 2 OCF(4)/OCF(4) SRL(3) SRH(3)
RETN SP+1 ---> SP+1 --->
RST p 1 OCF(5) SWH(3) SWL(3)
SP-1 ---> SP-1 --->
IN A,(n) 2 OCF(4) OD(3) PR(4)
IN r,(c) 2 OCF(4)/OCF(4) PR(4)
INI 2 OCF(4)/OCF(5) PR(4) MW(3)
IND
INIR 2 OCF(4)/OCF(5) PR(4) MW(3) IO(5)
INDR
OUT (n),A 2 OCF(4) OD(3) PW(4)
OUT (C),r 2 OCF(4)/OCF(4) PW(4)
OUTI 2 OCF(4)/OCF(5) MR(3) PW(4)
OUTD
OTIR 2 OCF(4)/0CF(5) MR(3) PW(4) I0(5)
OTDR
INTERRUPTS
----------
NMI _ OCF(5)* SWH(3) SWL(3) *Op Code Ignored
SP-1 ---> SP-1 --->
MODE 0 - INTA(6) ODL(3) ODH(4) SWH(3) SWL(3)
(CALL INSERTED) SP-1 ---> SP-1 --->
- INTA(6) SWH(3) SWL(3)
(RST INSERTED)
SP-1 ---> SP-1 --->
MODE 1 INTA(7) SWH(3) SWL(3)
(RST 38H
INTERNAL)
SP-1 ---> SP-1 --->
MODE 2 - INTA(7) SWH(3) SWL(3) MRL(3) MRH(3)
(VECTOR
SUPPLIED)
SP-1 ---> SP-1 --->
(
geocities.com/timessquare/arcade/2045/docs) (
geocities.com/timessquare/arcade/2045) (
geocities.com/timessquare/arcade) (
geocities.com/timessquare)