Yang Wu
46-54 Parsons Blvd.
Flushing, NY11355
(718) 661-4835
ptype@yahoo.com
Education:
State University of New York - Stony Brook, NY
M.S.E.E.: Jan 1997~Dec 1998
Overall GPA : 3.7/4.0
Objective:
Seeking a full-time position (starting from May 1998) in a challenging and
technically stimulating environment involved in
very high performance VLSI / ASIC system design.
Skills:
HDL & PL - VHDL, Verilog, C/C++, Java1.1, SQL, Perl, Visual Basic 5.0
Design Tools- Synopsys, ViewLogic, MAGIC, Hspice, Irsim, Visual Cafe 2.0
Operating Systems- Unix(On SUN Sparc), Windows NT, DOS/Windows
Project:
Using VHDL~
Cache behavior modeling
Booth Radix-4 Multiplier(synthesize)
16-bit CPU (DLX architecture) Simulation
Using Verilog(with Synopsys)~
Stack synthesize(and fitted into Altera MAXPlus II)
16-bit Processor (pipelined, RISC, simplified MIPS2000 architecture) Simulation
Using C/C++ language~
Simulation & Fault detecting of digital circuits
Image compressing using variable run-length coding (Huffman code)
Low pass filter for image processing
Banyan Network traffic simulation
Using Magic,Irsim,Hspice~
16-bit shift register using TSPC and CCMOS latch
4-bit pseudo-random number generator(using pseudostatic two-phase D-flip flop )
Using Java, JDBC~
1. On-Line shopping system - computer shop
(3 tiered architecture, with SSL support)
2. Restaurant Management System
(Decision support system)
Course Paper:
1. CDMA based Medium Acess Control Layer Protocol for Wireless ATM
2. Channel Assignment Techniques in Mobile Communication Systems
Special Training program:
Deep-Submicron VLSI system design engineer
--- taken from National Chin-Hua University, Taiwan,1996
Experience:
State University of New York, Teaching Assistant, Aug., 97 ~ Dec., 97
ESE318 Digital Logic Design, homework/exam grading, Lab section
United Microelectronics Company, Equipment Engineer, Jan, 94 ~
Oct, 96
Army, Infantry Lieutenant May, 92 ~ May, 94
Retired as a sub-captain