Requirements

• Simulate simple DLX pipeline structure: IF-ID-EX-MEM-WB.
• Simulate data forwarding and no data forwarding.
• Simulate branch delay and no branch delay.
• Simulate interleaving and non-interleaving memory (4 and 6 stalls.)
• Simulate cache and no cache.
• Simulate branch taken and not taken.
• Simulate branch target buffer and no branch target buffer.
• Calculate branch in ID stage.
• Instruction memory takes 1 cycle to read.
• Data range: -99.0 to +99.0
• Support integer and floating point operation (no DP).
• Execution unit takes only 1 cycle to execute any instruction.