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--**********************************************************************

--  - H/W Development Group

-- ************************************************************************

--

--  Title:     biu.vhd

--

--  Created:   Fri Aug 25 14:37:03 2000

--  Author:    Deepak George

--  Source File Name:   biu.vhd

--

--  $Id: biu.vhd,v 1.1 2000/08/25 14:37:03 acts Exp $

--

--  Description:   Basic Bus Interface Unit

--

--  Revision History:   1.0 v

--

--  $Log: biu.vhd,v $

--

-- ************************************************************************

 

library IEEE, STD;

use IEEE.std_logic_1164.all;

use IEEE.std_logic_components.all;

use IEEE.std_logic_arith.all;

use IEEE.std_logic_misc.all;

use IEEE.std_logic_unsigned.all;

 

entity biu is

  port     (addrin           : in   std_logic_vector(7 downto 0);

            clk              : in   std_logic;

            rst              : in   std_logic;

            mode             : in   std_logic;

            cs_b             : out  std_logic;

            oe_b             : out  std_logic;

            we_b             : out  std_logic;

            addrout          : out  std_logic_vector(7 downto 0)

           );

end biu;

 

architecture biu_A of biu is

 

signal mode_i           : std_logic_vector (2 downto 0);

signal count            : interger range 0 to 7;

signal cs_i             : std_logic;

signal oe_i             : std_logic;

signal we_i             : std_logic;

signal addri            : std_logic_vector(7 downto 0);

begin

 

gen : process(clk,rst,mode)

 

begin

if (rst = '1') then

 

  cs_i<= '1';

  oe_i<= '1';

  we_i<= '1';

  count<= 0;

elsif(clk'event and clk='1') then

 

  addri<= addrin;

 

  case mode is

    when "00" =>

      cs_i<= '0';

      oe_i<= '0';

      we_i<= '1';

     

    when "01" =>

      if (count = 7) then

        oe_i<= '1';

        cs_i<= '1';

        we_i<= '1';

      else

        cs_i<= '0';

        oe_i<= '0';

        we_i<= '1';

        count<=count + 1;

        addri<=addri + 1;

      end if;

     

    when "10" =>

      cs_i<= '0';

      oe_i<= '1';

      we_i<= '0';

     

    when others =>

      cs_i<='0';

      oe_i<='0';

      we_i<='0';

     

  end case;

   

end if;

 

end process;

 

addrout<= addri;

cs_b<= cs_i;

oe_b<= oe_i;

we_b< we_b;

 

end biu_A;

 

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