pllsstcsch

ELECTRIC SCHEMAS

The PLL driver circuit. The frequency and the frequency range depends by C6-7, R12 and R11. My secondary resonate at 360 kHz. For a better tuning I put a 10 kohms potentiometer in serie with R12. The frequency locking is made with the left 10 kohms potentiometer decreasing the voltage on the 10 nF cap from 12 V to 0 V, until the frequency locks. I used for this job a little neon tube, adjusting the potentiometer, with full DC input (40-50 VDC), until the brightness in the tube is at maximum and i have spark output. The LM 7812 has to be mounted on a little heatsink. The antenna is a 20-30 cm insulated wire (it can be much shorter). I first powered the logic circuit with a rectifyed 12 V@40 VA transformer, but the LM heat too much. I than change with two- three 9 V batteries in serie, with good results. The A, B ends are connected to the gate drive transformer primary.

THE GATE DRIVE TRANSFORMER it is a little cilindrical ferrite from monitor power cable. I made 5 windings ( one primary and 4 secondaries) , 12 turns each, with 0.5 mm magnet wire, twisted together, to diminuate the leakage inductance.

The original schema built by Steve Connor is

HERE

FULL BRIDGE WITH IRFP460 FETs (next project)

HALF BRIDGE WITH IRFP460 FETs
This is what I am using for now.

I used only 2 secondary windings from the gate drive transformer.

SCHEMA (I made a new GDT for the half bridge, 3 windings of 12 turns, on a ferrite toroid).

I calculated a 4.7 nF value for a resonant primary cap. I used a 5 nF instead because i just found it around.

I am using now a 1.33 uF at the driver output, instead 0.33 uF for more current.