//
// fifologic.V
// 
// FIFOLOGIC provides the interface to interact with the FIFO module.
// FIFO module is actually a 16*32 bits RAM. 
// The module instantiate 'FIFO.v'
// FIFOLOGIC has the ability to handle push and pop signals, even if 
// they occur simultaneously.


module fifologic(
             FCLK,             //Clock with frequency twice that of BCLK(200 MHz).
             FIFO_MODE,        //High for reception mode. 
             push,             //Write signal to FIFO
             pop,              //Read signal to FIFO.
             reset_n,          //
             TCL_IN,           //Input from transaction control logic
             TCL_OUT,          //Output to transaction  control logic.
             RT_IN,			   //Input from receiver
			 RT_OUT,           //Output to transmitter
			 status,		   //High when FIFO is not empty,			
			 fmode			   //High for reception mode.            
            );


input [31:0] TCL_IN,RT_IN;
wire  [31:0] TCL_IN,RT_IN;
output[31:0] TCL_OUT,RT_OUT;
wire   [31:0] TCL_OUT,RT_OUT;

input FCLK, push, pop, FIFO_MODE, reset_n;
wire  FCLK, push, pop, FIFO_MODE, reset_n;

output status;

reg [3:0] counter_W,counter_R;


output fmode;
reg status;
reg    fmode,RE,WE,WE_disable,push_save;
reg	[31:0] latch;
reg		  latch_signal;		

wire [3:0] Address;
wire [31:0] Q,Data;
assign Address = (WE) ? counter_W : counter_R;
assign Data = (fmode) ? RT_IN : TCL_IN;


// Instiation of FIFO RAM.
fifo f1(Address, FCLK, FCLK,WE, Data, Q);


always @(posedge FCLK or negedge reset_n)
begin
   if(!reset_n)
     status <= 1'b0;
   else 
    if(counter_W != counter_R)
		status <= 1'b1; 
	else if( (counter_R == counter_W) && !push_save )
	 	status <= 1'b0;
	 		
end

// Address of the current available empty location.
always @(negedge WE or negedge reset_n)
begin
   if(!reset_n)
     counter_W <= 4'h0;
   else 
     counter_W <= counter_W + 1;
end

// Generation of read enable signal to FIFO. 
always @(negedge FCLK or negedge reset_n)
begin
   if(!reset_n)
     RE <= 1'b0;
   else if(pop)
     RE <= 1'b1;
   else
     RE <= 1'b0;
end

//Address of the location first written. 
always @(negedge RE or negedge reset_n)
begin
   if(!reset_n)
     counter_R <= 4'h0; 
   else
     counter_R <= counter_R + 1;
end

// Latch the requested data until another pop signal.
always @(negedge FCLK)
begin
	if(latch_signal)
	begin
		latch_signal <= 1'b0;
		latch <= Q;
	end
	else if(pop)
		latch_signal <= 1'b1;
end

// Disable write signal if push and pop occur simultaneously.
always @(pop)
begin
   if(pop)
     WE_disable <= 1'b1;
   else
     WE_disable <= 1'b0;
end

// Write enable signal to FIFO.
always @(negedge FCLK)
begin
   if(push_save && !WE_disable)
     WE <= 1'b1;
   else
     WE <= 1'b0;
end

// Save the push request for simultaneous push and pop operations. 
always @(posedge push or posedge WE)
begin
   if(WE)
     push_save <= 1'b0;
   else
     push_save <= 1'b1;
end

// Save the fifo mode until reception of packet is complete.
always @(negedge FCLK or negedge reset_n)
begin
	if(!reset_n)
		fmode <= 1'b0;
	else if(FIFO_MODE == 0 && status == 0)
		fmode <= 1'b0;
	else if(FIFO_MODE)
		fmode <= FIFO_MODE;
end

// Routing of requested data according to fifo mode.
assign TCL_OUT = fmode ? latch : 32'h00000000 ;
assign RT_OUT  = fmode ? 32'h00000000  : latch; 


endmodule