module bismillah //tcl_fifologic_irs(//Inputs
						 (BCLK, FCLK, reset_n, CS_n, RDWR, ADDR_TLI, FIFO_MODE, 
						 RT_IN, pop_tr, push_tr, CA_n, RT_OUT, status, DATA_TLI, 
						 wenable_rx, oenable_dec, ADDR_IR_Rx_dec, DATA_IR_out, 
						 DATA_IR_Rx_in,TCL_OUT);
input BCLK, FCLK, reset_n, CS_n, RDWR, FIFO_MODE, pop_tr, push_tr;
input [7:0]ADDR_TLI, ADDR_IR_Rx_dec;
input [31:0]RT_IN;
input [15:0]DATA_IR_Rx_in;
wire [15:0]DATA_IR_in;
wire [7:0]ADDR_IR;
output CA_n, status;
output [31:0]RT_OUT,TCL_OUT;

reg [31:0]RT_OUT;
inout [31:0]DATA_TLI;

output [15:0]DATA_IR_out;

wire [31:0]DATA_OUT, DATA_IN, TCL_OUT;
input wenable_rx, oenable_dec;
wire push, pop, push_tcl, pop_tcl, wenable_rx, oenable_dec;

tcl TCL1(//Inputs
		   BCLK, CS_n, RDWR, ADDR_TLI, DATA_IN, 
           //Outputs		 
           CA_n, push_tcl, pop_tcl, wenable_tcl, oenable_tcl, 
		   fmode,//Input
		   DATA_TLI, //Inout
		   DATA_OUT /*out- data from tcl to IRs and fifomux*/);

fifologic FIFOLOGIC1(//Inputs
             FCLK, FIFO_MODE, push, pop, reset_n, /*TCL_IN =*/DATA_OUT,   
             TCL_OUT,//Output          
			 RT_IN,
			 //Output
			 RT_OUT, status, fmode);
irs IRS1(//Inputs
			BCLK, reset_n, wenable, oenable, ADDR_IR, /*DATA_IR_in =*/DATA_IR_in, 
        	//Output
			DATA_IR_out);
muxx MUXX1(reset_n, pop_tcl, oenable_tcl, TCL_OUT, DATA_IR_out, DATA_IN);

assign oenable = oenable_dec | oenable_tcl;
assign wenable = wenable_rx | wenable_tcl;

assign DATA_IR_in = (wenable_tcl) ? DATA_OUT[15:0]:DATA_IR_Rx_in;
assign ADDR_IR = (oenable_tcl || wenable_tcl) ? ADDR_TLI : ADDR_IR_Rx_dec;

or G1(pop, pop_tr, pop_tcl);
or G2(push, push_tr, push_tcl);

endmodule