// IRS.V
//
// The internal registers control the operation of the Link Layer Controller. 
// The register definitions and their respective addresses are specified as follows
//
// (All addresses are in hexadecimal)
//
//10-ATAck (Address Transmitter Acknowledge Receive)
//14-Ack Valid
//16-Ack Error
//17-TEn (Transmitter Enable)
//18-REn (Receiver Enable)
//19-HdrErr (Header CRC Error)
//1A-TcErr (Transaction Code Error)
//20-RdPhy (Read Phy-chip register)
//21-WrPhy (Write Phy-chip register)
//24-PhyRgAd (Physical-chip Register Address)
//28-PhyRgData (Physical-chip Register data)
//30-PhyRxAd (Physical-chip Register receive address)
//34-PhyRxData (Physical Chip Register receive data)
//40-Bus Number
//4A-Node Number
//50-Cycle Time Register


module irs(
		//Inputs
		BCLK, 
		reset_n, 
		wenable, //write enable-to enable memory for a write
		oenable, //output enable-to enable memory for a read
		ADDR_IR, //Input address of the register
		DATA_IR_in, //Data input to be written
		//Output
        DATA_IR_out //Data output to be read
	   );

input BCLK, wenable, oenable, reset_n;
wire BCLK, wenable, oenable, reset_n;
input [7:0] ADDR_IR;
wire [7:0] ADDR_IR;
input [15:0]DATA_IR_in;
wire [15:0]DATA_IR_in;
output [15:0]DATA_IR_out;

reg [15:0]DATA_IR_out;


reg [15:0]IR_0, IR_1, IR_2, IR_3, IR_4; //Registers serving as a storage for control info of Link Layer

always@(negedge BCLK or negedge reset_n)
begin

  if(!reset_n) //Initializing the internal registers whenever the Link Layer is reset
   begin
   IR_0<=16'h0000; 
   IR_1<=16'h0000; 
   IR_2<=16'h0000; 
   IR_3<=16'h0000;
   IR_4<=16'h0000;
   end

   else if(wenable) //Write to the Registers
   begin

   case(ADDR_IR)
   8'b 01000000: IR_0[15:0] <=DATA_IR_in[15:0];
   8'b 01001010: IR_0[5:0] <= DATA_IR_in[15:10];
   8'b 00010000: IR_1[15:12] <= DATA_IR_in[15:12];
   8'b 00010100: IR_1[11:10] <= DATA_IR_in[15:14];
   8'b 00010110: IR_1[9] <=  DATA_IR_in[15];
   8'b 00010111: IR_1[8] <=  DATA_IR_in[15];
   8'b 00011000: IR_1[7] <=  DATA_IR_in[15];
   8'b 00011001: IR_1[6] <=  DATA_IR_in[15];
   8'b 00011010: IR_1[8] <=  DATA_IR_in[15];
   8'b 00100000: IR_2[15] <= DATA_IR_in[15];
   8'b 00100001: IR_2[14] <= DATA_IR_in[15];
   8'b 00100100: IR_2[11:8] <= DATA_IR_in[15:12];
   8'b 00101000: IR_2[7:0] <= DATA_IR_in[15:8];
   8'b 00110000: IR_3[15:12] <= DATA_IR_in[15:12];
   8'b 00110100: IR_3[11:4] <= DATA_IR_in[15:8];
   8'b 01010000: IR_4 = DATA_IR_in;
   endcase
   
   end
   
   else if(oenable) //Read data from the internal registers
   case(ADDR_IR)
   8'b 01000000: DATA_IR_out[15:0] <= IR_0[15:0];
   8'b 01001010: DATA_IR_out[15:10] <= IR_0[5:0] ;
   8'b 00010000: DATA_IR_out[15:12] <= IR_1[15:12];
   8'b 00010100: DATA_IR_out[15:14] <= IR_1[11:10];
   8'b 00010110: DATA_IR_out[15] <= IR_1[9];
   8'b 00010111: DATA_IR_out[15] <= IR_1[8];
   8'b 00011000: DATA_IR_out[15] <= IR_1[7];
   8'b 00011001: DATA_IR_out[15] <= IR_1[6];
   8'b 00011010: DATA_IR_out[15] <= IR_1[5];
   8'b 00100000: DATA_IR_out[15] <= IR_2[15];
   8'b 00100001: DATA_IR_out[15] <= IR_2[14];
   8'b 00100100: DATA_IR_out[15:12] <= IR_2[11:8];
   8'b 00101000: DATA_IR_out[15:8] <= IR_2[7:0];
   8'b 00110000: DATA_IR_out[15:12] <= IR_3[15:12];
   8'b 00110100: DATA_IR_out[15:8] <= IR_3[11:4];
   8'b 01010000: DATA_IR_out <= IR_4;	
   default: DATA_IR_out<=16'h0000;
   
   endcase

end

endmodule