module muxx(reset_n, pop, oenable, TCL_OUT, DATA_IR_out, DATA_IN);

input pop, oenable, reset_n;
input [31:0]TCL_OUT, DATA_IR_out;
output [31:0]DATA_IN;
wire [31:0]DATA_IN;

reg route;

assign DATA_IN = route ? DATA_IR_out : TCL_OUT;



always @(posedge pop or posedge oenable or negedge reset_n)
begin
if(!reset_n)route<=0;
else if(oenable)route<=1;
else route<=0;
end

endmodule