//
// tcl.v (transaction control logic)
// The TCL module is used to provide an interface between the PINK and transaction layer
// The TCL uses the CS_n and RDWR signals to write and read data from FIFO and 
// Internal Registers. This logic generates the 'push' and 'pop' signals for FIFO and, 
// 'wenable' and 'oenable' signals for Internal Registers


module tcl( 
			 //Inputs
		     BCLK, //Bus clock. BCLK is the host bus clock used in the host-interface module of the
				   //Link Layer. It is asynchronous to SCLK.
			 CS_n, //Chip Select. Active Low signal. This signal is asserted low when  
				   //the Transaction Layer wants to issue a command.
             RDWR, //This signal specifies whether the Transaction Layer requests a read 
				   //or a write. HIGH=read, LOW=write.
		     ADDR_TLI, //The address given by the Transaction Layer to read or write from 
					   //a specific register of the LLC. For FIFO the ADDR_TLI = '00h'
	    	 DATA_IN, //Input Data from the FIFO and Internal Registers
             
			 //Outputs		 
             CA_n, //(1) CA_n is like an interrupt to the tr. layer. This notifies tr. layer 
				  //that the requested command has been executed and/or the relevant 
				  //results are ready on the host bus.
				  //(2) this is Out directly from FIFO to Tr Layer, only when we are 
				  //communicating with fifo. In the case of csrs ie. wenable and oenable
				  //the tli is responsible of providing CA_n to the tr. layer
				  //(3) we shall use an OR gate with i/ps both from FIFO and TLI itself 
				  //depending on CSR operation, ie. wenable and oenable
				  //therefore  CA_n = fifo_busy | CA_n_from_TLI;
             push, //This signal is generated to write data to the top of the FIFO.
             pop,  //To read data from the top of the FIFO this signal is used.
             wenable, //The TCL generates the wenable signal if a write to the Internal Registers is required.
             oenable, //The TCL generates the oenable signal if a read from the Internal Registers is required.
			 fmode, //input: Indicates that FIFO is in reception mode.
			 DATA_TLI, //Inout :This is a 32-bit bi-directional bus. The data to be read or to be written by the transaction layer is placed on this bus.
             

			 DATA_OUT //out- data from tli to CSR and fifomux

             );

input  BCLK,CS_n,RDWR,fmode;
wire   BCLK,CS_n,RDWR,fmode;
input  [31:0]DATA_IN;
wire   [31:0]DATA_IN;
output push,pop,wenable,oenable;
reg    push,pop,wenable,oenable;
reg    oenable_signal;
output CA_n;
wire   CA_n;

output [31:0]DATA_OUT;
reg    [31:0]DATA_OUT;
inout  [31:0]DATA_TLI;
wire   [31:0]DATA_TLI; 
input  [7:0] ADDR_TLI;
wire   [7:0] ADDR_TLI;

assign CA_n=push | pop | wenable | oenable;
assign DATA_TLI = (fmode || oenable || oenable_signal) ? DATA_IN : 32'hzzzzzzzz;


always @(posedge BCLK)
begin
	if(!CS_n)
		DATA_OUT <= DATA_TLI;
end

always@(posedge BCLK )
begin
	if(push)
		push <= 1'b0;
	else if(!CS_n && !RDWR && ADDR_TLI == 8'h00)  //push
	    push <= 1'b1;
end

always @(posedge BCLK)
begin
	if(wenable)
		wenable <= 1'b0;
	else if(!CS_n && !RDWR && ADDR_TLI != 8'h00)//wenable
		wenable <= 1'b1;	
end

always @(posedge BCLK)
begin
	if(oenable)
		oenable <= 1'b0;
	else if(!CS_n && RDWR && ADDR_TLI != 8'h00) //oenable
		oenable<=1;
end

always @(posedge BCLK)
begin
	if(pop)
		pop <= 1'b0;
	else if(!CS_n && RDWR && ADDR_TLI == 8'h00)
		pop <= 1'b1;
end

always @(negedge BCLK)
begin
	if(oenable_signal)
		oenable_signal <= 1'b0;
	else if(oenable)
		oenable_signal <= 1'b1;
end

endmodule