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3D GPU
Bluetooth Transceiver
Old Projects
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| Fall 2003-2004 |
| Digital
Engineering Lab |
| Led a team of 4 people in implementing a 3D
Graphics Processing Unit (GPU) on Xilinx XSV-800 FPGA
operating at 12.5 MHz with a resolution of 256 x 480. A
16 bit Float Point 5 stage Pipelined RISC Processor capable of
processing more than 1000 vertices/second and a Rasterizer pipeline
having a throughput close to 1 pixel /
clock cycle were designed. 34% FPGA resource usage. (3D
GPU) |
| Fall 2002-200 |
| Digital
Circuit Testing |
| Developed an efficient
test set for a circuit of approx 10,000 gates capable to of not only
detecting the stuck at faults but also pinpointing the locations of those
faults in circuit. (Report) |
| VLSI
Systems Design |
| Transistor
level design, simulation and layout (in 0.35mm technology) of a 4-Stage Pipelined Programmable
Digital Filter with a throughput of 166Msamples/s using Mentor
graphics and simulation with Eldo (a spice simulator) shows that the
system meets the constraints like delay and area. (Report)
|
| Applied
Communications System |
| Designed a Low Noise Amplifier
(LNA) for Bluetooth Transceiver, which provides a gain of
12 dB, for a noise figure (NF) of 2.84dB and an input referred IP3 of
+7.39 dBm. (Report) |
| Spring 2001-2002 |
| Computer
Architecture |
| Design and Implementation of a 16-bit RISC Processor (WISC-SP02 Architecture)
using Mentor Graphics’ Design Architect and Simulation using Quicksim
for performance parameters speed and cost of the design.
|
| Digital
Circuit & Components Design |
| Designed
a 16 bit Multiplier using Mentor Graphic's standard cell design
flow in 0.35mm |
| Analog
CMOS Integrated Circuit Design |
| Analog
Multiplier and OpAmp Design & Implementation in 0.5mm CMOS
technology using Tanner Tools. An Opamp with gain of 75dB and a bandwidth
of 450Mhz was designed. |
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